VR4102 datasheet(117/701 Pages) NEC

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CHAPTER 5 MEMORY MANAGEMENT SYSTEM

The VR4102 provides a memory management unit (MMU) which uses a translation lookaside buffer (TLB) to

translate virtual addresses into physical addresses. This chapter describes the virtual and physical address spaces,

the virtual-to-physical address translation, the operation of the TLB in making these translations, and the CP0

registers that provide the software interface to the TLB.

5.1 TRANSLATION LOOKASIDE BUFFER (TLB)

Virtual addresses are translated into physical addresses using an on-chip TLB 22. The on-chip TLB is a fully-

associative memory that holds 32 entries, which provide mapping to 32 odd/even page pairs for one entry. The

pages can have five different sizes, 1 K, 4 K, 16 K, 64 K, and 256 K, and can be specified in each entry. If it is

supplied with a virtual address, each of the 32 TLB entries is checked simultaneously to see whether they match the

virtual addresses that are provided with the ASID field and saved in the EntryHi register.

If there is a virtual address match, or “hit,” in the TLB, the physical page number is extracted from the TLB and

concatenated with the offset to form the physical address.

If no match occurs (TLB “miss”), an exception is taken and software refills the TLB from the page table resident in

memory.

The software writes to an entry selected using the Index register or a random entry indicated in the

Random register.

If more than one entry in the TLB matches the virtual address being translated, the operation is undefined and the

TLB may be disabled. In this case, the TLB-Shutdown (TS) bit of the Status register is set to 1, and the TLB

becomes unusable (an attempt to access the TLB results in a TLB Mismatch exception regardless of whether there

is an entry that hits). The TS bit can be cleared only by a reset.

Note that virtual addresses may be converted to physical addresses without using a TLB, depending on the

address space that is being subjected to address translation. For example, address translation for the kseg0 or

kseg1 address space does not use mapping. The physical addresses of these address spaces are determined by

subtracting the base address of the address space from the virtual addresses.

5.2 VIRTUAL ADDRESS SPACE

The address space of the CPU is extended in memory management system, by converting (translating) huge

virtual memory addresses into physical addresses.

The physical address space of the VR4102 is 4 Gbytes and 32-bit width addresses are used.

For the virtual address space, up to 2 Gbytes (2

31) are provided as a user’s area and 32-bit width addresses are

used in the 32-bit mode. In the 64-bit mode, up to 1 Tbyte (2

40) is provided as a user’s area and 64-bit width

addresses are used. For the format of the TLB entry in each mode, refer to 5.4.1.

As shown in Figures 4-2 and 4-3, the virtual address is extended with an address space identifier (ASID), which

reduces the frequency of TLB flushing when switching contexts. This 8-bit ASID is in the CP0 EntryHi register, and

the Global (G) bit is in the EntryLo0 and EntryLo1 registers, described later in this chapter.

VR4102 Datasheet(PDF) 117 Page - NEC