VR4102 datasheet(114/701 Pages) NEC

114 / 701 page

CHAPTER 4 VR4102 PIPELINE

114

4.5.3 Slip Conditions

During

)2 of the RF stage and )1 of the EX stage, internal logic will determine whether it is possible to start the

current instruction in this cycle. If all of the source operands are available (either from the register file or via the

internal bypass logic) and all the hardware resources necessary to complete the instruction will be available

whenever required, then the instruction “run”; otherwise, the instruction will “slip”. Slipped instructions are retired on

subsequent cycles until they issue. The backend of the pipeline (stages DC and WB) will advance normally during

slips in an attempt to resolve the conflict. NOPs will be inserted into the bubble in the pipeline. Instructions killed by

branch likely instructions, ERET or exceptions will not cause slips.

Figure 4-15. Load Data Interlock

ADD A, B

Load B

Load A

Bypass

Detect load interlock

Get the target data

Load Data Interlock is detected in the RF stage shown in as Figure 4-15 and also the pipeline slips in the stage.

Load Data Interlock occurs when data fetched by a load instruction and data moved from HI, LO or CP0 register is

required by the next immediate instruction. The pipeline begins running again when the clock after the target of the

load is read from the data cache, HI, LO and CP0 register. The data returned at the end of the DC stage is input into

the end of the RF stage, using the bypass multiplexers.

Figure 4-16. MD Busy Interlock

MFLO/MFHI

Bypass

Detect MD busy interlock

Get target data

VR4102 Datasheet(PDF) 114 Page - NEC