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VR4102 Datasheet(PDF) 113 Page - NEC

Part # VR4102
Description  64/32-bit Microprocessor
PDF  701 Pages
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Manufacturer  NEC [NEC]
Direct Link  http://www.nec.com/
Logo NEC - NEC

VR4102 Datasheet(HTML) 113 Page - NEC

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CHAPTER 4 VR4102 PIPELINE
113
4.5.2 Stall Conditions
Stalls are used to stop the pipeline for conditions detected after the RF stage. When a stall occurs, the processor
will resolve the condition and then the pipeline will continue. Figure 4-13 shows a data cache miss stall, and Figure
4-14 shows a CACHE instruction stall.
Figure 4-13. Data Cache Miss Stall
1
Detect data cache miss
IF
RF
EX
DC
WB
WB
WB
WB
WB
IF
RF
EX
DC
DC
DC
DC
DC
WB
IF
RF
EX
EX
EX
EX
EX
DC
WB
IF
RF
RF
RF
RF
RF
EX
DC
WB
2
3
1
Start moving data cache line to write buffer
2
Get last word into cache and restart pipeline
3
If the cache line to be replaced is dirty
• the W bit is set • the data is moved to the internal write buffer in the
next cycle. The write-back data is returned to memory. The last word in the data is returned to the cache at 3, and
pipelining restarts.
Figure 4-14. CACHE Instruction Stall
1
CACHE instruction start
IF
RF
EX
DC
WB
WB
WB
WB
WB
IF
RF
EX
DC
DC
DC
DC
DC
WB
IF
RF
EX
EX
EX
EX
EX
DC
WB
IF
RF
RF
RF
RF
RF
EX
DC
WB
2
1
CACHE instruction complete
2
When the CACHE instruction enters the DC pipe-stage, the pipeline stalls while the CACHE instruction is
executed. The pipeline begins running again when the CACHE instruction is completed, allowing the instruction
fetch to proceed.



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