VR4102 datasheet(115/701 Pages) NEC

115 / 701 page

CHAPTER 4 VR4102 PIPELINE

115

MD Busy Interlock is detected in the RF stage as shown in Figure 4-16 and also the pipeline slips in the stage.

MD Busy Interlock occurs when Hi/Lo register is required by MFHi/Lo instruction before finishing Mult/Div execution.

The pipeline begins running again the clock after finishing Mult/Div execution. The data returned from the Hi/Lo

Store-Load Interlock is detected in the EX stage and the pipeline slips in the RF stage. Store-Load Interlock

occurs when store instruction followed by load instruction is detected. The pipeline begins running again one clock

after.

Coprocessor 0 Interlock is detected in the EX stage and the pipeline slips in the RF stage.

A coprocessor

interlock occurs when an MTC0 instruction for the Configuration or Status register is detected.

The pipeline begins running again one clock after.

4.5.4 Bypassing

In some cases, data and conditions produced in the EX, DC and WB stages of the pipeline are made available to

the EX stage (only) through the bypass data path.

Operand bypass allows an instruction in the EX stage to continue without having to wait for data or conditions to

be written to the register file at the end of the WB stage. Instead, the Bypass Control Unit is responsible for ensuring

data and conditions from later pipeline stages are available at the appropriate time for instructions earlier in the

pipeline.

The Bypass Control Unit is also responsible for controlling the source and destination register addresses supplied

to the register file.

4.6 CODE COMPATIBILITY

The VR4100 CPU core can execute all programs that can be executed in other VR-Series processors. But the

reverse is not necessarily true. Programs complied using a standard MIPS compiler can be executed in both types

of processors. When using manual assembly, however, write programs carefully so that compatibility with other VR-

series processors can be maintained. Matters which should be paid attention to when porting programs between the

VR4100 CPU core and other VR-Series processors are listed below.

• The V

4100 CPU core does not support floating-point instructions since it has no Floating-Point Unit (FPU).

• Multiply-add instructions (DMADD16, MADD16) are added in the V

4100 CPU core.

• Instructions for power modes (HIBERNATE, STANDBY, SUSPEND) are added in the V

4100 CPU core to

support power modes.

• The V

4100 CPU core does not have the LL bit to perform synchronization of multiprocessing. Therefore, the

CPU core does not support instructions which manipulate the LL bit (LL, LLD, SC, SCD).

• The CP0 hazards of the V

4100 CPU core are equally or less stringent than those of other processors (see

Chapter 28 for details).

For more information, refer to Chapter 27,

the VR4000, VR4400 User’s Manual, or the VR4200

TM User’s Manual.

VR4102 Datasheet(PDF) 115 Page - NEC

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