VR4102 datasheet(130/701 Pages) NEC

130 / 701 page

CHAPTER 5 MEMORY MANAGEMENT SYSTEM

130

Table 5-3. 32-bit Kernel Mode Segments

Address bit value

Status register bit value

Segment

Virtual address

Physical

Size

KSU

EXL

ERL

name

address

32-bit

A[31] = 0

kuseg

0x0000 0000

0x7FFF FFFF

TLB map

2 Gbytes

31 bytes)

32-bit

A[31..29] = 100

kseg0

0x8000 0000

0x9FFF FFFF

0x0000 0000

0x1FFF FFFF

512 Mbytes

29 bytes)

32-bit

A[31..29] = 101

kseg1

0xA000 0000

0xBFFF FFFF

0x0000 0000

0x1FFF FFFF

512 Mbytes

29 bytes)

32-bit

A[31..29] = 110

ksseg

0xC000 0000

0xDFFF FFFF

TLB map

512 Mbytes

29 bytes)

32-bit

A[31..29] = 111

KSU = 00

EXL = 1

ERL = 1

kseg3

0xE000 0000

0xFFFF FFFF

TLB map

512 Mbytes

29 bytes)

(1) kuseg (32-bit Kernel mode, user space)

When KX = 0 in the Status register, and the most-significant bit of the virtual address space is 0, the kuseg

virtual address space is selected; it is the current 2-Gbyte (2

31-byte) user address space.

The virtual address is extended with the contents of the 8-bit ASID field to form a unique virtual address.

References to kuseg are mapped through TLB. Whether cache can be used or not is determined by bit C of

each page’s TLB entry.

If the ERL bit of the Status register is 1, the user address space is assigned 2 Gbytes (2

31 bytes) without TLB

mapping and becomes unmapped (with virtual addresses being used as physical addresses) and uncached so

that the cache error handler can use it. This allows the Cache Error exception code to operate uncached using

r0 as a base register.

(2) kseg0 (32-bit Kernel mode, kernel space 0)

When KX = 0 in the Status register and the most-significant three bits of the virtual address space are 100, the

kseg0 virtual address space is selected; it is the current 512-Mbyte (2

29-byte) physical space.

References to kseg0 are not mapped through TLB; the physical address selected is defined by subtracting

0x8000 0000 from the virtual address.

The K0 field of the Config register controls cacheability (see CHAPTER 6 EXCEPTION PROCESSING).

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