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P5021 Datasheet(PDF) 153 Page - NXP Semiconductors |
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P5021 Datasheet(HTML) 153 Page - NXP Semiconductors |
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153 / 155 page  Security fuse processor P5021 QorIQ Integrated Processor Data Sheet, Rev. 1 Freescale Semiconductor 153 5 Security fuse processor This chip implements the QorIQ platform’s Trust Architecture, supporting capabilities such as secure boot. Use of the Trust Architecture features is dependent on programming fuses in the Security Fuse Processor (SFP). The details of the Trust Architecture and SFP can be found in the applicable chip reference manual. To program SFP fuses, the user is required to supply 1.5 V to the POVDD pin per Section 2.2, “Power-up sequencing.” POVDD should only be powered for the duration of the fuse programming cycle, with a per device limit of two fuse programming cycles. All other times, connect POVDD to GND. The sequencing requirements for raising and lowering POVDD are shown in Figure 8. To ensure device reliability, fuse programming must be performed within the recommended fuse programming temperature range per Table 3. Users not implementing the QorIQ platform’s Trust Architecture features are not required to program fuses and should connect POVDD to GND. 6 Ordering information Please contact your local Freescale sales office or regional marketing team for ordering information. 6.1 Part numbering nomenclature This table provides the Freescale QorIQ platform part numbering nomenclature. Table 108. Part Numbering Nomenclature pn nn n x t e n c d r Generation Platform Number of Cores Derivative Qual Status Temperature Range Encryption Package Type CPU Speed DDR Speed Die Revision P=45 nm 5 • 01 = 1 core •02 = 2 cores •04 = 4 cores 0–9 P = Prototype N= Qualified •S = Std temp (0 °C to 105 °C •X = Ext temp (–40 °Cto 105 °C) •E = SEC present •N = SEC not present 1 = FC-PBGA lead-free 7= FC-PBGA C4/C5 lead-free •T = 1800 MHz •V = 2000 MHz •2 = 2200 MHz •M = 1200 MHz •N = 1333 MHz •Q = 1600 MHz A = Rev 1.0 B = Rev 2.0 C = Rev 2.1 |
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