P5021 datasheet(148/155 Pages) NXP

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P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Hardware design considerations

Freescale Semiconductor

148

3.6.3

Guidelines for high-speed interface termination

This section provides the guidelines for high-speed interface termination when the SerDes interface is entirely unused or when

it is partly unused.

3.6.3.1

SerDes interface entirely unused

If the high-speed SerDes interface is not used at all, the unused pin should be terminated as described in this section.

The following pins must be left unconnected:

•

SD_TX[19:0]

•SD_TX[19:0]

•SD_IMP_CAL_RX

•

SD_IMP_CAL_TX

•

SD1_IMP_CAL_RX

•

SD1_IMP_CAL_TX

The following pins must be connected to SGND:

•

SD_RX[19:0]

•SD_RX[19:0]

•

SD_REF_CLK1, SD_REF_CLK2, SD_REF_CLK3, SD_REF_CLK4

•

SD_REF_CLK1, SD_REF_CLK2, SD_REF_CLK3, SD_REF_CLK4

The RCW configuration fields SRDS_LPD_B1, SRDS_LPD_B2, SRDS_LPD_B3, and SRDS_LPD_B4, all bits must be set to

power down all the lanes in each bank.

The RCW configuration field SRDS_EN may be cleared to power down the SerDes block for power saving. Setting

RCW[SRDS_EN_S1] = 0 powers down the PLLs of banks 1 to 3; RCW[SRDS_EN_S2]=0 powers down the PLL of bank 4.

Additionally, software may configure SRDSBnRSTCTL[SDRD] = 1 for the unused banks to power down the SerDes bank

PLLs to save power.

Note that both SVDD and XVDD must remain powered.

3.6.3.2

SerDes interface partly unused

If only part of the high speed SerDes interface pins are used, the remaining high-speed serial I/O pins should be terminated as

described in this section.

The following pins must be left unconnected:

•SD_TX[n]

The following unused pins must be connected to SGND:

•SD_RX[n]

•

SD_REF_CLK1, SD_REF_CLK1 (If entire SerDes bank 1 unused)

•

SD_REF_CLK2, SD_REF_CLK2 (If entire SerDes bank 2 unused)

•

SD_REF_CLK3, SD_REF_CLK3 (If entire SerDes bank 3 unused)

•

SD_REF_CLK4, SD_REF_CLK4 (If entire SerDes bank 4 unused)

P5021 Datasheet(PDF) 148 Page - NXP Semiconductors

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