P5021 datasheet(117/155 Pages) NXP

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Electrical characteristics

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

117

2.20.5.2.3

XAUI receiver AC timing specifications

This table defines the receiver AC specifications for XAUI. RefClk jitter is not included.

This figure shows the single-frequency sinusoidal jitter limits.

Figure 44. Single-Frequency Sinusoidal Jitter Limits

Table 74. XAUI receiver AC timing specifications

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Typical

Max

Unit

Notes

Deterministic jitter tolerance

0.37

—

UI p-p

Combined deterministic and random

jitter tolerance

JDR

0.55

—

UI p-p

Total jitter tolerance

0.65

—

UI p-p

1, 2

Bit error rate

BER

—

10–12

——

Unit Interval: 3.125 GBaud

320 – 100 ppm

320

320 + 100 ppm

—

Notes:

1. Measured at receiver

2. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The

sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 44. The sinusoidal jitter component

is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects.

8.5 UI p-p

0.10 UI p-p

Sinusoidal

jitter

amplitude

22.1 kHz

1.875 MHz

20 MHz

Frequency

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