P5021 datasheet(121/155 Pages) NXP

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Electrical characteristics

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

121

This table provides the Gen2i or 3 Gbits/s differential receiver input DC characteristics for the SATA interface.

2.20.7.2

SATA AC timing specifications

This section discusses the SATA AC timing specifications.

2.20.7.2.1

AC requirements for SATA REF_CLK

The AC requirements for the SATA reference clock are listed in this table to be guaranteed by the customer’s application design.

Table 82. Gen2i/3 G receiver Input DC specifications (XVDD = 1.5 V or 1.8 V)

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Typical

Max

Units

Notes

Differential input voltage

VSATA_RXDIFF

275

—

750

mV p-p

Differential receiver input impedance

ZSATA_RXSEIM

100

115

OOB signal detection threshold

VSATA_OOB

120

240

mV p-p

Notes:

1. Voltage relative to common of either signal comprising a differential pair

2. DC impedance

Table 83. SATA reference clock input requirements

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Typ

Max

Unit

Notes

SD_REF_CLK/SD_REF_CLK frequency range

tCLK_REF

—

100/125

—

MHz

SD_REF_CLK/SD_REF_CLK clock frequency tolerance

tCLK_TOL

–350

—

+350

ppm

—

SD_REF_CLK/SD_REF_CLK reference clock duty cycle

tCLK_DUTY

SD_REF_CLK/SD_REF_CLK cycle-to-cycle clock jitter (period jitter)

tCLK_CJ

—

100

SD_REF_CLK/SD_REF_CLK total reference clock jitter, phase jitter

(peak-peak)

tCLK_PJ

–50

—

+50

2, 3, 4

Notes:

1. Caution: Only 100, and 125 MHz have been tested. In-between values do not work correctly with the rest of the system.

2. At RefClk input

3. In a frequency band from 150 kHz to 15 MHz at BER of 10-12

4. Total peak-to-peak deterministic jitter should be less than or equal to 50 ps.

5. Measurement taken from differential waveform

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