P5021 datasheet(125/155 Pages) NXP

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Electrical characteristics

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

125

Output differential voltage2, 3, 4

(XVDD-Typ at 1.5 V and 1.8 V)

|VOD|

320

500.0

725.0

B(1-3)TECR(lane)0[AMP_RED]

=0b000000

293.8

459.0

665.6

B(1-3)TECR(lane)0[AMP_RED]

=0b000010

266.9

417.0

604.7

B(1-3)TECR(lane)0[AMP_RED]

=0b000101

240.6

376.0

545.2

B(1-3)TECR(lane)0[AMP_RED]

=0b001000

213.1

333.0

482.9

B(1-3)TECR(lane)0[AMP_RED]

=0b001100

186.9

292.0

423.4

B(1-3)TECR(lane)0[AMP_RED]

=0b001111

160.0

250.0

362.5

B(1-3)TECR(lane)0[AMP_RED]

=0b010011

Output impedance (single-ended)

—

Notes:

1. This does not align to DC-coupled SGMII.

2. |VOD| = |VSD_TXn– VSD_TXn|. |VOD| is also referred to as output differential peak voltage. VTX-DIFFp-p = 2*|VOD|.

3. Example amplitude reduction setting for SGMII on SerDes bank 1 lane E: B1TECRE0[AMP_RED] = 0b000010 for an output

differential voltage of 459 mV typical.

4. The |VOD| value shown in the Typ column is based on the condition of XVDD_SRDSn-Typ = 1.5 V or 1.8 V, no common mode

offset variation. SerDes transmitter is terminated with 100-

Ω differential load between SD_TXn and SD_TXn.

Table 88. SGMII DC transmitter electrical characteristics (XVDD = 1.5 V or 1.8 V) (continued)

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Typ

Max

Unit

Notes

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