P5021 datasheet(127/155 Pages) NXP

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Electrical characteristics

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

127

This table defines the SGMII 2.5x transmitter DC electrical characteristics for 3.125 GBaud.

2.20.8.1.2

SGMII DC receiver electrical characteristics

This table lists the SGMII DC receiver electrical characteristics for 1.25 GBaud. Source synchronous clocking is not supported.

Clock is recovered from the data.

This table defines the SGMII 2.5x receiver DC electrical characteristics for 3.125 GBaud.

2.20.8.2

SGMII AC timing specifications

This section discusses the AC timing specifications for the SGMII interface.

Table 89. SGMII 2.5x transmitter DC electrical characteristics (XVDD = 1.5 V or 1.8 V)

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Typical

Max

Unit

Notes

Output voltage

–0.40

—

2.30

Differential output voltage

VDIFFPP

800

—

1600

mV p-p

—

Note:

1. Absolute output voltage limit

Table 90. SGMII DC receiver electrical characteristics (XVDD = 1.5 V or 1.8 V)

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Typ

Max

Unit

Notes

DC Input voltage range

—

N/A

—

Input differential voltage

REIDL_CTL = 001xx

VRX_DIFFp-p

100

—

1200

2, 4

REIDL_CTL = 100xx

175

—

Loss of signal threshold

REIDL_CTL = 001xx

VLOS

—

100

3, 4

REIDL_CTL = 100xx

—

175

Receiver differential input impedance

ZRX_DIFF

—

120

—

Notes:

1. Input must be externally AC coupled.

2. VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage.

3. The concept of this parameter is equivalent to the electrical idle detect threshold parameter in PCI Express. See

Section 2.20.4.4, “PCI Express DC physical layer receiver specifications,” and Section 2.20.4.5.2, “PCI Express AC physical

layer receiver specifications,” for further explanation.

4. The REIDL_CTL shown in the table refers to the chip’s SerDes control register B(1-3)GCR(lane)1[REIDL_CTL] bit field.

Table 91. SGMII 2.5x receiver DC timing specifications (XVDD = 1.5 V or 1.8 V)

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Typical

Max

Unit

Notes

Differential input voltage

VIN

200

900

1600

mV p-p

Note:

1. Measured at the receiver.

P5021 Datasheet(PDF) 127 Page - NXP Semiconductors

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