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MMPF0100 Datasheet(PDF) 106 Page - NXP Semiconductors

Part # MMPF0100
Description  14 channel configurable power management integrated circuit
PDF  136 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MMPF0100 Datasheet(HTML) 106 Page - NXP Semiconductors

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NXP Semiconductors
PF0100
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.5.5
Specific registers
6.5.5.1
IC and version identification
The IC and other version details can be read via identification bits. These are hard-wired on chip and described in Tables 129 to 131.
6.5.5.2
Embedded memory
There are four register banks of general purpose embedded memory to store critical data. The data written to MEMA[7:0], MEMB[7:0],
MEMC[7:0], and MEMD[7:0] is maintained by the coin cell when the main battery is deeply discharged, removed, or contact-bounced. The
contents of the embedded memory are reset by COINPORB. The banks can be used for any system need for bit retention with coin cell
backup.
VGEN5FAULTS
4
R
0
VGEN5 overcurrent sense bit
• 0 = Normal operation
• 1 = Above current limit
VGEN6FAULTS
5
R
0
VGEN6 overcurrent sense bit
• 0 = Normal operation
• 1 = Above current limit
UNUSED
7:6
–
00
unused
Table 129. Register DEVICEID - ADDR 0x00
Name
Bit #
R/W
Default
Description
DEVICEID
3:0
R
0x00
Die version.
• 0000 = PF0100
UNUSED
7:4
–
0x01
unused
Table 130. Register SILICON REV- ADDR 0x03
Name
Bit #
R/W
Default
Description
METAL_LAYER_REV
3:0
R
0x00
Represents the metal mask revision
• Pass 0.0 = 0000
• .
• .
• Pass 0.15 = 1111
FULL_LAYER_REV
7:4
R
0x01
Represents the full mask revision
• Pass 1.0 = 0001
• .
• .
• Pass 15.0 = 1111
Table 131. Register FABID - ADDR 0x04
Name
Bit #
R/W
Default
Description
FIN
1:0
R
0x00
Allows for characterizing different options within
the same reticule
FAB
3:2
R
0x00
Represents the wafer manufacturing facility
Unused
7:0
R
0x00
unused
Table 128. Register INTSENSE4 - ADDR 0x13 (continued)
Name
Bit #
R/W
Default
Description



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