LM5145 datasheet(35/69 Pages) TI

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The ESR of a capacitor is provided in the manufacturer’s data sheet either explicitly as a specification or

implicitly in the impedance versus frequency curve. Depending on type, size, and construction, electrolytic

capacitors have significant ESR, 5 mΩ and above, and relatively large ESL, 5 nH to 20 nH. PCB traces

contribute some parasitic resistance and inductance as well. Ceramic output capacitors, on the other hand, have

low ESR and ESL contributions at the switching frequency, and the capacitive impedance component dominates.

However, depending on the package and voltage rating of the ceramic capacitor, the effective capacitance can

drop quite significantly with applied DC voltage and operating temperature.

Ignoring the ESR term in Equation 17 gives a quick estimation of the minimum ceramic capacitance necessary

to meet the output ripple specification. Two to four 47-µF, 10-V, X7R capacitors in 1206 or 1210 footprint is a

common choice for a 5-V output. Use Equation 18 to determine if additional capacitance is necessary to meet

the load-off transient overshoot specification.

A composite implementation of ceramic and electrolytic capacitors highlights the rationale for paralleling

capacitors of dissimilar chemistries yet complementary performance. The frequency response of each capacitor

is accretive in that each capacitor provides desirable performance over a certain portion of the frequency range.

While the ceramic provides excellent mid-frequency and high-frequency decoupling characteristics with its low

ESR and ESL to minimize the switching frequency output ripple, the electrolytic device with its large bulk

capacitance provides low-frequency energy storage to cope with load transient demands.

10.1.1.3 Input Capacitors

Input capacitors are necessary to limit the input ripple voltage to the buck power stage due to switching-

frequency AC currents. TI recommends using X7S or X7R dielectric ceramic capacitors to provide low

impedance and high RMS current rating over a wide temperature range. To minimize the parasitic inductance

in the switching loop, position the input capacitors as close as possible to the drain of the high-side MOSFET

and the source of the low-side MOSFET. Use Equation 19 to calculate the input capacitor RMS current for a

single-channel buck regulator.

CIN,rms

OUT

1 D

(19)

The highest input capacitor RMS current occurs at D = 0.5, at which point the RMS current rating of the input

capacitors is greater than half the output current.

Ideally, the DC component of input current is provided by the input voltage source and the AC component by the

input filter capacitors. Neglecting inductor ripple current, the input capacitors source current of amplitude (IOUT −

IIN) during the D interval and sink IIN during the 1−D interval. Thus, the input capacitors conduct a square-wave

current of peak-to-peak amplitude equal to the output current. It follows that the resultant capacitive component

of AC ripple voltage is a triangular waveform. Together with the ESR-related ripple component, use Equation 20

to calculate the peak-to-peak ripple voltage amplitude.

OUT

ESR

(20)

Use Equation 21 to calculate the input capacitance required for a particular load current, based on an input

voltage ripple specification of ΔVIN.

OUT

ESR

OUT

1 D

˜ '

(21)

Low-ESR ceramic capacitors can be placed in parallel with higher valued bulk capacitance to provide optimized

input filtering for the regulator and damping to mitigate the effects of input parasitic inductance resonating

with high-Q ceramics. One bulk capacitor of sufficiently high current rating and four 10-μF 50-V X7R ceramic

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