LM5145 datasheet(22/69 Pages) TI

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• tOFF(min) is the minimum off time of 60 ns.

9.3.6 Clock Synchronization (DEMB)

To synchronize the LM25143 to an external source, apply a logic-level clock signal (greater than 2 V) to DEMB.

The LM25143 can be synchronized to ±20% of the programmed frequency up to a maximum of 2.5 MHz. If there

is an RT resistor and a synchronization signal, the LM25143 ignores the RT resistor and synchronizes to the

external clock. Under low VIN conditions when the minimum off time is reached, the synchronization signal is

ignored, allowing the switching frequency to reduce to maintain output voltage regulation.

9.3.7 Synchronization Out (SYNCOUT)

The SYNCOUT voltage is a logic level signal with a rising edge approximately 90° lagging HO2 (or 90° leading

HO1). When the SYNCOUT signal is used to synchronize a second LM25143 controller, all four phases are 90°

out of phase.

9.3.8 Spread Spectrum Frequency Modulation (DITH)

The LM25143 provides a frequency dithering option that is enabled by connecting a capacitor from DITH to

AGND. This generates a triangular voltage centered at 1.2 V at DITH. See Figure 9-2. The triangular waveform

modulates the oscillator frequency by ±5% of the nominal frequency set by the RT resistance. Use Equation 3

to calculate the required DITH capacitance to set the modulating frequency, FMOD. For the dithering circuit to

effectively attenuate the peak EMI, the modulation rate must be less than 20 kHz for proper operation of the

clock circuit.

(3)

DITH

AGND

1.25 V

1.15 V

1.2 V

Figure 9-2. Switching Frequency Dithering

If DITH is connected to VDDA during power up, the dither feature is disabled and cannot be enabled unless VCC

is recycled below the VCC UVLO threshold. If DITH is connected to AGND on power up, CDITH is prevented from

charging, disabling dither. Also, dither is disabled when the LM25143 is synchronized to an external clock.

9.3.9 Configurable Soft Start (SS1, SS2)

The soft-start feature allows the regulator to gradually reach the steady-state operating point, thus reducing

start-up stresses and surges.

The LM25143 features an adjustable soft start that determines the charging time of the output or outputs.

Soft-start limits inrush current as a result of high output capacitance to avoid an overcurrent condition. Stress on

the input supply rail is also reduced.

The LM25143 regulates the FB voltage to the SS voltage or the internal 600-mV reference, whichever is lower.

At the beginning of the soft-start sequence when the SS voltage is 0 V, the internal 21-μA soft-start current

source gradually increases the voltage on an external soft-start capacitor connected to the SS pin, resulting in a

gradual rise of the relevant FB and output voltages. Use Equation 4 to calculate the soft-start capacitance.

LM25143

SNVSC10 – MARCH 2022

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