LM5145 datasheet(51/69 Pages) TI

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10.2.3 Design 3 – Two-Phase, 50-A, 300-kHz Single-Output Buck Regulator for ASIC Power Applications

Figure 10-24 shows the schematic diagram of a single-output, two-phase synchronous buck regulator with an

output voltage of 5 V. The expected DC load current is 35 A with transients up to 50 A. In this example, the

target efficiency at 35 A is 96% using a power stage optimized for a nominal input voltage of 24 V. The switching

frequency is set at 300 kHz by resistor RRT, and inductor DCR current sensing is used to mitigate shunt-related

losses at high current. The 5-V output is connected to VCCX to reduce IC bias power dissipation and improve

light-load efficiency. An output voltage of 3.3 V is also feasible simply by connecting FB1 to VDDA.

VIN = 18 V...36 V

(24 V nom)

SS2 RES

DEMB

AGND SS1

COMP2

PGND2

VOUT2

CS2

LO2

SW2

HO2

HB2

VIN

COMP1

PGND1

VOUT1

CS1

LO1

SW1

HO1

HB1

VCC

PG1

HOL1

LOL1

HOL2

LOL2

EN1

EN2

VCCX

VDDA

PG2

SYNCOUT

VIN

LM25143

LO1

CO2

CIN

CSS

CRES

CVDDA

LO2

CO1

RS2

CDITH

DITH

RRT

0.47 F

10 F

10 nF

47 F

10 nF

1.5 H

47 F

10 k

1.5 H

2.2 F

73.2 k

RC1

CC1

6.8 nF

4.99 k

CVCC2

2.2 F

CVCC1

CVCCX

2.2 F

DB1

0.1 F

CBST1

0.1 F

CBST2

DB2

0.47 F

FB1

FB2 MODE

VDDA

CS2

0.1 F

RS1

10 k

CS1

0.1 F

CC2

150 pF

220 F

CO(BULK)

CIN(BULK)

LIN

1.5 H

10 F

100 F

VOUT = 5 V

IOUT = 35 A (TDC)

= 50 A (EDC)

VDDA

Figure 10-24. Application Circuit 3 With LM25143 Two-Phase Buck Regulator at 300 kHz

10.2.3.1 Design Requirements

Table 10-6 shows the intended input, output, and performance parameters for this design example.

Table 10-6. Design Parameters

Design Parameter

Value

Nominal input voltage

24 V

Input voltage range (steady state)

18 V to 36 V

Output voltage

5 V

Thermal design current (TDC)

35 A

Electrical design current (EDC)

50 A

Switching frequency

300 kHz

Output voltage regulation

±1%

Shutdown current

4 µA

The switching frequency is set at 300 kHz by resistor RRT. In terms of control loop performance, the target loop

crossover frequency is 45 kHz with a phase margin greater than 50°. The output voltage soft-start time is set at

3 ms by a 100-nF soft-start capacitor. FPWM operation provides constant switching frequency over the full load

current range for predictable EMI performance and optimal load transient response.

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LM25143

SNVSC10 – MARCH 2022

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