LM5145 datasheet(57/69 Pages) TI

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12.2 Layout Example

Based on the LM5143-Q1EVM-2100 design, Figure 12-2 shows a single-sided layout of a dual-output

synchronous buck regulator. Each power stage is surrounded by a GND pad geometry to connect an EMI

shield if needed. The design uses layer 2 of the PCB as a power-loop return path directly underneath the top

layer to create a low-area switching power loop of approximately 2 mm². This loop area, and hence parasitic

inductance, must be as small as possible to minimize EMI as well as switch-node voltage overshoot and ringing.

Refer to the LM5143-Q1EVM-2100 Evaluation Module User's Guide for more detail.

Locate the controller close to the power stage ±

keep gate drive traces short and direct

Use paralleled 0603

input capacitors close

to the FETs for VIN to

PGND decoupling

EMI S-filter with

electroytic cap for

parallel admping

VOUT

VIN

GND

GND pad

geometry for EMI

shield connection

Copper island

connected to AGND pin

Keep the VCC and

BOOT caps close to

their respective pins

Optional jumper to connect VOUT1 and

VOUT2 for a 2-phase implementation

Figure 12-2. PCB Top Layer

As shown in Figure 12-3, the high-frequency power loop current of one channel flows through MOSFETs Q2

and Q4, through the power ground plane on layer 2, and back to VIN through the 0603 ceramic capacitors

C16 through C19. The currents flowing in opposing directions in the vertical loop configuration provide field

self-cancellation, reducing parasitic inductance. Figure 12-4 shows a side view to illustrate the concept of

creating a low-profile, self-canceling loop in a multilayer PCB structure. The layer-2 GND plane layer, shown in

Figure 12-3, provides a tightly-coupled current return path directly under the MOSFETs to the source terminals of

Q2.

Four 10-nF input capacitors with small 0402 or 0603 case size are placed in parallel very close to the drain

of each high-side MOSFET. The low equivalent series inductance (ESL) and high self-resonant frequency

(SRF) of the small footprint capacitors yield excellent high-frequency performance. The negative terminals of

these capacitors are connected to the layer-2 GND plane with multiple 12-mil (0.3-mm) diameter vias, further

minimizing parasitic loop inductance.

Additional steps used in this layout example include:

• Keep the SW connection from the power MOSFETs to the inductor (for each channel) at minimum copper

area to reduce radiated EMI.

• Locate the controller close to the gate terminals of the MOSFETs such that the gate drive traces are routed

short and direct.

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