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Use internal layer or layers as ground plane or planes. Pay particular attention to shielding the feedback (FB)

trace from power traces and components.

• Locate the upper and lower feedback resistors (if required) close to the respective FB pins, keeping the FB

traces as short as possible. Route the trace from the upper feedback resistor or resistors to the required

output voltage sense point or points at the load or loads.

• Route the CS1/2 and VOUT1/2 traces as differential pairs to minimize noise pickup and use Kelvin

connections to the applicable shunt resistor (if shunt current sensing is used) or to the sense capacitor

(if inductor DCR current sensing is used).

• Minimize the loop area from the VCC1/2 and VIN pins through their respective decoupling capacitors to the

relevant PGND pins. Locate these capacitors as close as possible to the LM25143.

12.1.4 Thermal Design and Layout

The useful operating temperature range of a PWM controller with integrated gate drivers and bias supply LDO

regulator is greatly affected by the following:

• Average gate drive current requirements of the power MOSFETs

• Switching frequency

• Operating input voltage (affecting bias regulator LDO voltage drop and hence its power dissipation)

• Thermal characteristics of the package and operating environment

For a PWM controller to be useful over a particular temperature range, the package must allow for the efficient

removal of the heat produced while keeping the junction temperature within rated limits. The LM25143 controller

is available in a small 6-mm × 6-mm 40-pin VQFN (RHA) PowerPAD package to cover a range of application

requirements. The summarizes the thermal metrics of this package.

The 40-pin VQFNP package offers a means of removing heat from the semiconductor die through the exposed

thermal pad at the base of the package. While the exposed pad of the package is not directly connected to any

leads of the package, it is thermally connected to the substrate of the LM25143 device (ground). This allows a

significant improvement in heat sinking, and it becomes imperative that the PCB is designed with thermal lands,

thermal vias, and a ground plane to complete the heat removal subsystem. The exposed pad of the LM25143 is

soldered to the ground-connected copper land on the PCB directly underneath the device package, reducing the

thermal resistance to a very low value.

Numerous vias with a 0.3-mm diameter connected from the thermal land to the internal and solder-side ground

plane or planes are vital to help dissipation. In a multilayer PCB design, a solid ground plane is typically placed

on the PCB layer below the power components. Not only does this provide a plane for the power stage currents

to flow but it also represents a thermally conductive path away from the heat generating devices.

The thermal characteristics of the MOSFETs also are significant. The drain pads of the high-side MOSFETs are

normally connected to a VIN plane for heat sinking. The drain pads of the low-side MOSFETs are tied to the

respective SW planes, but the SW plane area is purposely kept as small as possible to mitigate EMI concerns.

12.1.5 Ground Plane Design

As mentioned previously, using one or more of the inner PCB layers as a solid ground plane is recommended. A

ground plane offers shielding for sensitive circuits and traces and also provides a quiet reference potential for the

control circuitry. Connect the PGND1 and PGND2 pins to the system ground plane using an array of vias under

the exposed pad. Also connect the PGND1 and PGND2 pins directly to the return terminals of the input and

output capacitors. The PGND nets contain noise at the switching frequency and can bounce because of load

current variations. The power traces for PGND1/2, VIN and SW1/2 can be restricted to one side of the ground

plane. The other side of the ground plane contains much less noise and is ideal for sensitive analog trace routes.

LM25143

SNVSC10 – MARCH 2022

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