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Table 7-55. GPIO Timing Conditions (continued)

PARAMETER

BUFFER TYPE

MIN

MAX UNIT

OUTPUT CONDITIONS

Output load capacitance

LVCMOS

I2C OD FS

100

Table 7-56. GPIO Timing Requirements

NO.

PARAMETER

DESCRIPTION

BUFFER TYPE

MIN

MAX

UNIT

GPIO1 tw(GPIO_IN)

Pulse width, GPIOn_x

LVCMOS

2P + 2.6(1)

I2C OD FS

2P + 2.6(1)

(1)

P = functional clock period in ns.

Table 7-57. GPIO Switching Characteristics

NO.

PARAMETER

DESCRIPTION

BUFFER TYPE

MIN

MAX

UNIT

GPIO2 tw(GPIO_OUT)

Pulse width, GPIOn_x

LVCMOS

0.975P(1) -

3.6

I2C OD FS

160

(1)

P = functional clock period in ns.

For more information, see General-Purpose Interface (GPIO) section in Peripherals chapter in the device TRM.

7.10.5.10 GPMC

For more details about features and additional description information on the device General-Purpose Memory

Controller, see the corresponding subsections within Signal Descriptions and Detailed Description sections.

Table 7-58 presents timing conditions for GPMC.

Table 7-58. GPMC Timing Conditions

PARAMETER

MIN

MAX UNIT

INPUT CONDITIONS

SRI

Input slew rate

1.65

V/ns

OUTPUT CONDITIONS

Output load capacitance

PCB CONNECTIVITY REQUIREMENTS

td(Trace Delay)

Propagation delay of each trace

133 MHz Synchronous Mode

140

360

All other modes

140

720

td(Trace Mismatch

Delay)

Propagation delay mismatch across all traces

200

For more information, see General-Purpose Memory Controller (GPMC) section in Peripherals chapter in the

device TRM.

7.10.5.10.1 GPMC and NOR Flash — Synchronous Mode

Table 7-59 and Table 7-60 present timing requirements and switching characteristics for GPMC and NOR Flash -

Synchronous Mode.

AM625, AM623

SPRSP58 – JUNE 2022

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