AM625 datasheet(137/235 Pages) TI

137 / 235 page

Table 7-60. GPMC and NOR Flash Switching Characteristics – Synchronous Mode (continued)

see Figure 7-45, Figure 7-46, Figure 7-47, Figure 7-48, and Figure 7-49

NO.

(2)

PARAMETER

DESCRIPTION

MODE(16)

MIN

MAX

MIN

MAX

UNIT

100 MHz

133 MHz

F14 td(clkH-wen)

Delay time, output clock GPMC_CLK

rising edge to output write enable

GPMC_WEn transition

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1;

no extra_delay

I - 2.3

(8)

I + 4.5

I - 2.3

(8)

I + 4.5

F15 td(clkH-do)

Delay time, output clock GPMC_CLK

rising edge to output data

GPMC_AD[15:0] transition(10)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

J - 2.3

(9)

J + 2.7

J - 2.3

(9)

J + 2.7

F15 td(clkL-do)

Delay time, GPMC_CLK falling

edge to GPMC_AD[15:0] data bus

transition(11)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

J - 2.3

(9)

J + 2.7

J - 2.3

(9)

J + 2.7

F15 td(clkL-do).

Delay time, GPMC_CLK falling

edge to GPMC_AD[15:0] data bus

transition(12)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

J - 2.3

(9)

J + 2.7

J - 2.3

(9)

J + 2.7

F17 td(clkH-be[x]n)

Delay time, output clock GPMC_CLK

rising edge to output lower byte

enable and command latch enable

GPMC_BE0n_CLE transition(10)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

J - 2.3

(9)

J + 1.9

J - 2.3

(9)

J + 1.9

F17 td(clkL-be[x]n)

Delay time, GPMC_CLK falling edge

to GPMC_BE0n_CLE, GPMC_BE1n

transition(11)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

J - 2.3

(9)

J + 1.9

J - 2.3

(9)

J + 1.9

F17 td(clkL-be[x]n).

Delay time, GPMC_CLK falling edge

to GPMC_BE0n_CLE, GPMC_BE1n

transition(12)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

J - 2.3

(9)

J + 1.9

J - 2.3

(9)

J + 1.9

F18 tw(csnV)

Pulse duration, output chip select

GPMC_CSn[i](13) low

Read

Write

F19 tw(be[x]nV)

Pulse duration, output lower byte

enable and command latch enable

GPMC_BE0n_CLE, output upper byte

enable GPMC_BE1n low

Read

Write

F20 tw(advnV)

Pulse duration, output address

valid and address latch enable

GPMC_ADVn_ALE low

Read

Write

(1)

For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

With n being the page burst access number.

(2)

B = ClkActivationTime × GPMC_FCLK(14)

(3)

For single read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

For burst read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

For burst write: D = (WrCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

(4)

For single read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

For burst read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

For burst write: E = (CSWrOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

(5)

For csn falling edge (CS activated):

•

Case GPMCFCLKDIVIDER = 0:

–

F = 0.5 × CSExtraDelay × GPMC_FCLK(14)

•

Case GPMCFCLKDIVIDER = 1:

–

F = 0.5 × CSExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and

CSOnTime are even)

–

F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(14) otherwise

•

Case GPMCFCLKDIVIDER = 2:

–

F = 0.5 × CSExtraDelay × GPMC_FCLK(14) if ((CSOnTime - ClkActivationTime) is a multiple of 3)

–

F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(14) if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)

–

F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK(14) if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)

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