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7.10.5.13 MCASP

Table 7-68, Table 7-69, Figure 7-61, Table 7-70, and Figure 7-62 present timing conditions, requirements, and

switching characteristics for MCASP.

Table 7-68. MCASP Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

0.7

V/ns

OUTPUT CONDITIONS

Output load capacitance

PCB CONNECTIVITY REQUIREMENTS

td(Trace Delay)

Propagation delay of each trace

100

1100

td(Trace Mismatch Delay)

Propagation delay mismatch across all traces

100

Table 7-69. MCASP Timing Requirements

see Figure 7-61

NO.

MODE(1)

MIN

MAX UNIT

ASP1 tc(AHCLKRX)

Cycle time, MCASP[x]_AHCLKR/X(4)

ASP2 tw(AHCLKRX)

Pulse duration, MCASP[x]_AHCLKR/X(4) high or low

0.5P(2) -

1.53

ASP3 tc(ACLKRX)

Cycle time, MCASP[x]_ACLKR/X(4)

ASP4 tw(ACLKRX)

Pulse duration, MCASP[x]_ACLKR/X(4) high or low

0.5R(3) -

1.53

ASP5 tsu(AFSRX-ACLKRX)

Setup time, MCASP[x]_AFSR/X(4) input valid before

MCASP[x]_ACLKR/X(4)

ACLKR/X int

9.29

ACLKR/X ext in/out

ASP6 th(ACLKRX-AFSRX)

Hold time, MCASP[x]_AFSR/X(4) input valid after

MCASP[x]_ACLKR/X(4)

ACLKR/X int

-1

ACLKR/X ext in/out

1.6

ASP7 tsu(AXR-ACLKRX)

Setup time, MCASP[x]_AXR(4) input valid before

MCASP[x]_ACLKR/X(4)

ACLKR/X int

9.29

ACLKR/X ext in/out

ASP8 th(ACLKRX-AXR)

Hold time, MCASP[x]_AXR(4) input valid after

MCASP[x]_ACLKR/X(4)

ACLKR/X int

-1

ACLKR/X ext in/out

1.6

(1)

ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1

ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0

ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1

ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1

ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0

ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1

(2)

P = AHCLKR/X period in ns.

(3)

R = ACLKR/X period in ns.

(4)

x in MCASP[x]_* is 0, 1 or 2

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SPRSP58 – JUNE 2022

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