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AM625 Datasheet(PDF) 154 Page - Texas Instruments |
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AM625 Datasheet(HTML) 154 Page - Texas Instruments |
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154 / 235 page  GPMC_FCLK GPMC_CSn[i] GPMC_BE0n_CLE GPMC_ADVn_ALE GPMC_OEn_REn GPMC_WEn DATA GNF0 GNF1 GNF4 GNF9 GNF3 GNF6 GPMC_AD[15:0] GPMC_15 A. `In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. Figure 7-59. GPMC and NAND Flash — Data Write Cycle 7.10.5.11 I2C For more details about features and additional description information on the device Inter-Integrated Circuit, see the corresponding subsections within Signal Descriptions and Detailed Description sections. Section 7.10.5.11.1, Table 7-65 and Figure 7-60 assume testing over the recommended operating conditions and electrical characteristic conditions. 7.10.5.11.1 Timing Requirements for I2C Input Timings NO.(1) (6) PARAMETER DESCRIPTION MODE MIN MAX UNIT I1 tc(SCL) Cycle time, SCL Standard 10000 ns Fast 2500 ns I2 tsu(SCLH-SDAL) Setup time, SCL high before SDA low (for a repeated START condition) Standard 4700 ns Fast 600 ns I3 th(SDAL-SCLL) Hold time, SCL low after SDA low (for a START and a repeated START condition) Standard 4000 ns Fast 900 ns I4 tw(SCLL) Pulse duration, SCL low Standard 4700 ns Fast 1300 ns I5 tw(SCLH) Pulse duration, SCL high Standard 4000 ns Fast 600 ns I6 tsu(SDAV-SCLH) Setup time, SDA valid before SCL high Standard 250 ns Fast 100 (2) ns I7 th(SCLL-SDAV) Hold time, SDA valid after SCL low Standard 0(3) 3450(4) ns Fast 0(3) 900 (4) ns I8 tw(SDAH) Pulse duration, SDA high between STOP and START conditions Standard 4700 ns Fast 1300 ns I9 tr(SDA) Rise time, SDA Standard 1000 ns Fast 20*(Vdd/5.5 V)(5) (7) 300 (3) (7) ns I10 tr(SCL) Rise time, SCL Standard 1000 ns Fast 20*(Vdd/5.5 V)(5) (7) 300 (3) (7) ns AM625, AM623 SPRSP58 – JUNE 2022 www.ti.com 154 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AM625 AM623 |
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