MEC1632 datasheet(199/636 Pages) MICROCHIP

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DS00001592B-page 199

MEC1632

Setting the Port92 Enable bit (PORT92 Enable Register) enables the Port92h Register. When Port92 is disabled, by

clearing the Port92 Enable bit, then access to this register is completely disabled (I/O writes to host 92h are ignored and

I/O reads float the system data bus SD[7:0]).

ALT_CPU_RESET

This bit provides an alternate means to generate a CPU_RESET pulse. The CPU_RESET output provides a means to

reset the system CPU to effect a mode switch from Protected Virtual Address Mode to the Real Address Mode. This

provides a faster means of reset than is provided through the EC keyboard controller. Writing a “1” to this bit will cause

the ALT_RST# internal signal to pulse (active low) for a minimum of 6

s after a delay of 14s. Before another ALT_RST#

pulse can be generated, this bit must be written back to “0”.

ALT_GATEA20

This bit provides an alternate means for system control of the MEC1632 GATEA20 pin.

0=ALT_A20 is driven low

1=ALT_A20 is driven high

When Port 92 is enabled, writing a 0 to bit 1 of the PORT92 Register forces ALT_A20 low. ALT_A20 low drives GATEA20

low, if A20 from the keyboard controller is also low. When Port 92 is enabled, writing a 1 to bit 1 of the PORT92 Register

forces ALT_A20 high. ALT_A20 high drives GATEA20 high regardless of the state of A20 from the keyboard controller.

10.13.2

GATE A20

The MEC1632 contains on-chip logic support for the GATEA20 hardware speed-up feature. GATEA20 is part of the con-

trol required to mask address line A20 to emulate 8086 addressing.

In addition to the ability for the host to control the GATEA20 output signal directly, a configuration bit called “SAEN” (Soft-

ware Assist Enable, bit 1 of Keyboard Control Register is provided; when set, SAEN allows firmware to control the

GATEA20 output.

When SAEN is set, a 1 bit register (GATEA20 Control Register) controls the GATEA20 output. The register bit allocation

is shown in Table 10-13.

Note 10-7

Refer to the GATEA20 Control description for information on this register. This is a one bit register

(Bits 1-7=0 on read).

TABLE 10-16: PORT92 REGISTER

HOST I/O

ADDRESS

0092h

8-bit HOST SIZE

EC OFFSET

00h

8-bit EC SIZE

POWER

VTR

00h nSIO_RESET DEFAULT

BUS

LPC SPB

BYTE3 BIT

D7D6

D5D4

HOST TYPE

RR/W

R/W

EC TYPE

---

BIT NAME

Reserved

ALT_GATEA

ALT_CPU_

RESET

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