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MEC1632 Datasheet(PDF) 198 Page - Microchip Technology

Part # MEC1632
Description  Low Power 32-Bit Mobile Embedded Controller
PDF  636 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MEC1632 Datasheet(HTML) 198 Page - Microchip Technology

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MEC1632
DS00001592B-page 198
 2012-2018 Microchip Technology Inc.
Note 10-6
CMD is bit D3 in the Keyboard Status Read Register.
All Registers listed in Table 10-14 are powered by VTR and reset by nSYS_RST except the PORT92 Register which is
powered by VTR and reset by nSIO_RESET (See Section , "iRESET OUT," on page 133).
10.12 Configuration Registers
10.12.1
PORT 92 ENABLE
The MEC1632 supports LPC I/O writes to port 92h as a quick alternate mechanism for generating a CPU_RESET pulse
or controlling the state of GATEA20.
10.13 Runtime Registers
10.13.1
PORT 92
The MEC1632 supports LPC I/O writes to port HOST I/O address 92h as a quick alternate mechanism for generating a
CPU_RESET pulse or controlling the state of GATEA20.
The PORT92 Register resides at HOST I/O address 92h and is used to support the alternate reset (ALT_RST#) and
alternate GATEA20 (ALT_A20) functions. This register defaults to 00h on assertion of nSIO_RESET (See Section ,
"iRESET OUT," on page 133).
TABLE 10-14:
Port92-Legacy SUPPORT REGISTER SUMMARY
Host I/O Access
EC Interface
Register Name
Host I/O
Address
SPB Offset
Host
Type
SPB Offset
Byte
Lane
EC Type
Notes
GATEA20 Control
Register
--
-
100h
0
R/W
SETGA20L Register
--
-
108h
0
W
RSTGA20L Register
-
-
-
10Ch
0
W
PORT92 Register
92h
000h
R/W
000h
0
R/W
Host Access
EC Interface
Register Name
Host Config.
Index
SPB Offset
Host
Type
SPB
Offset
Byte
Lane
EC Type
PORT92 Enable
Register
30h
3F0h
R/W
330h
0
R/W
TABLE 10-15: PORT92 ENABLE REGISTER
HOST CONFIG
INDEX
30h
8-bit HOST SIZE
EC OFFSET
330h
8-bit EC SIZE
POWER
VTR
00h
nSYS_RST
DEFAULT
BUS
LPC SPB
BYTE3 BIT
D7D6D5
D4D3
D2
D1
D0
HOST TYPE
RR/W
EC TYPE
-
-
-
---
--
BIT NAME
Reserved
P92_EN



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