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MEC1632 Datasheet(PDF) 197 Page - Microchip Technology |
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MEC1632 Datasheet(HTML) 197 Page - Microchip Technology |
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197 / 636 page ![]() 2012-2018 Microchip Technology Inc. DS00001592B-page 197 MEC1632 10.9.2.1 Keyboard Control UD User defined bit AUXH Aux in Hardware; when high, AUXOBF of the status register is set in hardware by a write to EC OFFSET 10Ch. When low, AUXOBF of the status register is a user defined bit (UD) and R/W. OBFEN When set,PCOBF is gated onto KIRQ and AUXOBF1 is gated onto MIRQ. When low, KIRQ and MIRQ are driven low. Software should not change this bit when OBF of the status register is equal to 1. PCOBFEN When high, PCOBF reflects whatever value was written to the PCOBF firmware latch assigned to 114h. When low, PCOBF reflects the status of writes to EC OFFSET 100h (the output data register). SAEN Software-assist enable. When set to “1,” SAEN allows control of the GATEA20 signal via firmware. If SAEN is reset to ‘0’, GATEA20 corresponds to either the last host-initiated control of GATEA20 or the firmware write to EC OFFSETs 108h or 10Ch. 10.10 Legacy Support 10.11 Port92-Legacy Registers The Table 10-14 is a register summary for the Port92-Legacy block. The LPC I/O address of the PORT92 Register is fixed. Each EC address is indicated as an SPB Offset from its AHB base address listed for the Port92-Legacy block in Table 10-2, “8042 Emulated Keyboard Controller Base Address Table,” on page 192. Each Configuration register access through the Host Access Port address via its LDN indicated in Table 10-2 on page 192 and its Host Access Port index which is described as “Host Config Index” in the tables below. TABLE 10-13: KEYBOARD CONTROL REGISTER HOST OFFSET NA 8-bit HOST SIZE EC OFFSET 108h 8-bit EC SIZE POWER VTR 00h nSYS_RST DEFAULT BUS LPC SPB BYTE3 BIT D7D6 D5D4 D3D2D1 D0 HOST TYPE - - - --- -- EC TYPE R/WR/W R/WR/W R/WR/W R/WR/W BIT NAME AUXH UD OBFEN UD UD PCOB- FEN SAEN UD |
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