MEC1632 datasheet(196/636 Pages) MICROCHIP

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MEC1632

DS00001592B-page 196

 2012-2018 Microchip Technology Inc.

Additional flexibility has been added which allows firmware to directly control the PCOBF output signal, independent of

data transfers to the host-interface data output register. This feature allows the MEC1632 to be operated via the host

“polled” mode. This firmware control is active when PCOBFEN = 1 and firmware can then bring PCOBF high by writing

a “1” to the LSB of the 1 bit data register, PCOBF, at EC OFFSET 114h. The firmware must also clear this bit by writing

a “0” to the LSB of the 1 bit data register at EC OFFSET 114h.

The PCOBF register is also readable; bits 1-7 will return a “0” on the read back. The value read back on bit 0 of the

the firmware latch at EC OFFSET 114h. If PCOBFEN = 0, then the value read back reflects the in-process status of write

cycles to EC OFFSET 100h (i.e., if the value read back is high, the host interface output data register has just been

written to). If OBFEN=0, then KIRQ is driven inactive (low).

10.9.2

AUXOBF1 DESCRIPTION

(The following description assumes that OBFEN = 1 in Keyboard Control Register on page 197); This bit is multiplexed

onto MIRQ. The AUXOBF1/MIRQ signal is a system interrupt which signifies that the EC has written to the EC_HOST

Data / AUX Data Register.

On power-up, after nSYS_RST, AUXOBF1 is reset to 0. AUXOBF1 will normally reflects the status of writes to EC OFF-

SET 10Ch. (MIRQ is normally selected as IRQ12 for mouse support). AUXOBF1 is cleared by hardware on a read of

the Host Data Register. If OBFEN=0, then KIRQ is driven inactive (low).

TABLE 10-10: STATUS AND INTERRUPT BEHAVIOR OF WRITING TO OUTPUT DATA REGISTER

Host I/F Status Register Bits

Write to Register

AUXOBF (D5)

OBF (D0)

OBFEN=0

OBFEN=1

EC OFFSET 100h

KIRQ=0

KIRQ=1

EC OFFSET 10Ch

MIRQ=0

MIRQ=1

TABLE 10-11: OBFEN AND PCOBFEN EFFECTS ON KIRQ

OBFEN

PCOBFEN

KIRQ is inactive and driven low

KIRQ = PCOBF@EC OFFSET 100h

KIRQ = PCOBF@EC OFFSET 114h

TABLE 10-12: OBFEN AND AUXH EFFECTS ON MIRQ

OBFEN

AUXH

MIRQ is inactive and driven low

MIRQ = PCOBF@EC OFFSET 10Ch; Status Register D5 = User Defined

MIRQ = PCOBF@EC OFFSET 10Ch; Status Register D5 = Hardware Controlled

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