MEC1632 datasheet(200/636 Pages) MICROCHIP

200 / 636 page

MEC1632

DS00001592B-page 200

 2012-2018 Microchip Technology Inc.

10.13.3

GATEA20 CONTROL

GATEA20

Writing a “0” into bid GATEA20 causes the GATEA20 output to go low, and vice versa.

Host control and firmware control of GATEA20 affect two separate register elements. Read back of GATEA20 through

the use of EC OFFSET 100h reflects the present state of the GATEA20 output signal: if SAEN is set, the value read

back corresponds to the last firmware-initiated control of GATEA20; if SAEN is reset, the value read back corresponds

to the last host-initiated control of GATEA20.

Host control of the GATEA20 output is provided by the hardware interpretation of the “GATEA20 sequence” (see

Table 10-18). The foregoing description assumes that the SAEN configuration bit is reset.

When the MEC1632 receives a “D1” command followed by data (via the host interface), the on-chip hardware copies

the value of data bit 1 in the received data field to the GATEA20 host latch. At no time during this host-interface trans-

action will PCOBF or the IBF flag (bit 1) in the Keyboard Status Read Register be activated; for example, this host control

of GATEA20 is transparent to firmware, with no consequent degradation of overall system performance. Table 10-18

details the possible GATEA20 sequences and the MEC1632 responses.

On VCC_POR, GATEA20 will be set.

An additional level of control flexibility is offered via a memory-mapped synchronous set and reset capability. Any data

written to EC OFFSET 108h causes the GATEA20 host latch to be set; any data written to EC OFFSET 10Ch causes it

to be reset. This control mechanism should be used with caution. It was added to augment the “normal” control flow as

described above, not to replace it. Since the host and the firmware have asynchronous control capability of the host

latch via this mechanism, a potential conflict could arise. Therefore, after using the EC OFFSET 108h and EC OFFSET

10Ch addresses, firmware should read back the GATEA20 status via EC OFFSET 100h (with SAEN = 0) to confirm the

actual GATEA20 response.

TABLE 10-17: GATEA20 CONTROL REGISTER

HOST OFFSET

8-bit HOST SIZE

EC OFFSET

100h

8-bit EC SIZE

POWER

VTR

00h nSYS_RST

DEFAULT

BUS

LPC SPB

BYTE3 BIT

D7D6D5

D3D2D1

HOST TYPE

------

EC TYPE

RR/W

BIT NAME

Reserved

GATEA20

TABLE 10-18: GATEA20 COMMAND/DATA SEQUENCE EXAMPLES

Data

Byte

R/W

D[0:7]

IBF FLAG

GATEA20

Comments

GATEA20 Turn-on Sequence

GATEA20 Turn-off Sequence

GATEA20 Turn-on Sequence(*)

MEC1632 Datasheet(PDF) 200 Page - Microchip Technology

MEC1632 Datasheet(HTML) 200 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL