MEC1632 datasheet(193/636 Pages) MICROCHIP

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 2012-2018 Microchip Technology Inc.

DS00001592B-page 193

MEC1632

10.7

8042 MSG Interface Configuration Registers

10.7.1

ACTIVATE REGISTER

ACTIVATE

0=1MHz Clock to the CPU_REST block is disabled, ONLY if the PGEN is not active

1=1MHz Clock to the CPU_REST block is enabled

10.8

8042 MSG Interface Runtime Registers

10.8.1

HOST_EC DATA / CMD REGISTER

This is an 8-bit HOST write-only register. When written with Data, the C/D status bit of the status register is cleared to

zero and the IBF bit is set.

When written with a command, the C/D status bit of the status register is set to one and the IBF bit is set to a 1.

TABLE 10-4:

8042 MSG Interface ACTIVATE REGISTER

HOST CONFIG

INDEX

330h

8-bit HOST SIZE

EC OFFSET

8-bit EC SIZE

POWER

VTR

00h nSYS_RST

DEFAULT

BUS

LPC SPB

BYTE3 BIT

D7D6

D5D4

D3D2D1

HOST TYPE

RR/W

EC TYPE

---

BIT NAME

Reserved

Activate

TABLE 10-5:

HOST_EC DATA/CMD REGISTER

HOST I/O INDEX

00h Data

04h Command

8-bit HOST SIZE

EC OFFSET

100h

8-bit EC SIZE

POWER

VTR

00h nSYS_RST

DEFAULT

BUS

LPC SPB

BYTE3 BIT

D7D6

D5D4

D3D2D1

HOST TYPE

WWW

EC TYPE

RRR

BIT NAME

Data

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