MEC1632 datasheet(124/636 Pages) MICROCHIP

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MEC1632

DS00001592B-page 124

 2012-2018 Microchip Technology Inc.

7.5.3

POWER-UP SEQUENCE

Table 7-24 summarizes the MEC1632 Power-Up Sequence. For information regarding the typical relationships of the

MEC1632 power supplies to the system power states see Section 7.5, "Power Configuration," on page 121.

Note 7-37

for VTR-powered on-chip registers that are reset by VCC_PWRGD, it is important that firmware not

write to any of these registers until 1 ms following the assertion of VCC_PWRGD (‘1’).

7.6

Reset Interface

7.6.1

OVERVIEW

The primary function of the Reset Interface (Figure 7-18) is to generate VTR and VBAT reset signaling; including,

VTRGD, VBAT_POR, nSYS_RST, nEC_RST and Watch-Dog Timer Forced Reset (Table 7-25). The Reset Interface

also includes section regarding a RESET Pin Interface, and the 1.8V Regulator. There is other VCC-related Reset

Interface functionality not shown in Figure 7-18 that is described Section 7.7.2, "VCC Power Good," on page 129 and

Section 7.7.3, "LPC RESET," on page 129.

Also included in the Reset Interface are descriptions of the Power Mux and Registers Interface. These are related

Power, Clocks, and Resets functions that are not described anywhere else in this chapter.

7.6.2

STRAP OPTIONS

Note 7-38

This strap option is sampled on VTR power up, and is not affected by RESETI# or a WDT reset.

Note 7-39

This GPIO pin is sampled by the Boot ROM code following a VTR power up, and when RESETI# is

asserted.

TABLE 7-24:

Power-Up Sequence

VBAT

VTR

VCC

Reset Interface

Description

OFF

–

MEC1632 fully unpowered

OFF

–

32.768 KHz Silicon Oscillator may be disabled as

described in Section 7.6.5, "VBAT_POR," on

page 128.

OFF

VBAT_POR,

VTRGD,

nSYS_RST.

nEC_RST,

nSIO_RESET

VBAT-powered registers may be reset as

described in Section 7.6.5, "VBAT_POR," on

page 128. VTR-powered registers and blocks

reset (nSYS_RST). EC held in reset as

described in Section 7.6.7, "nEC_RST," on

page 128.

nSIO_RESET asserted.

20 MHz Oscillator enabled.

EC begins code execution following a delay as

described in Section 7.6.7, "nEC_RST," on

page 128.

VCC_PWRGD,

nSIO_RESET

Registers affected by VCC_PWRGD are reset

(Note 7-37)

Firmware de-asserts nSIO_RESET as described

in "iRESET OUT," on page 133.

TABLE 7-25:

VTR/VBAT RESET THRESHOLDS

Parameter

MIN

TYP

MAX

Units

Notes

VTRGD Reset Threshold

0.5

1.8

2.7

Volts

VBAT_POR Reset Threshold

0.5

1.25

1.9

TABLE 7-26:

STRAP OPTIONS

Name

Notes

Boundary Scan

GPIO171/MSDATA

Note 7-38

UART_BOOT_STRAP

GPIO166

Note 7-39

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