MEC1632 datasheet(126/636 Pages) MICROCHIP

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MEC1632

DS00001592B-page 126

 2012-2018 Microchip Technology Inc.

7.6.3

RESET PIN INTERFACE

7.6.3.1

RESETI#

As illustrated in Figure 7-19, when asserted (‘0’) the RESETI# input can force the equivalent of a VTRGD to the

MEC1632. The RESETI# input includes an analog glitch filter (Note 7-40). Timing for the RESETI# input is shown in

Figure 7-19 and Table 7-27.

The RESETI# input also affects the JTAG interface as defined in Section 44.7.3.1, "Async JTAG RESET," on page 586.

Note 7-40

The RESETI# input can tolerate glitches of no more than 50ns.

7.6.3.2

RESETO#

The RESETO# output pin GPIO062/RESETO# defaults to an output ‘low’ following a VTR power up, or assertion of the

RESETI# input pin. Firmware de-asserts RESETO# by making the GPIO062 output ‘high’.

7.6.4

VTRGD

VTRGD is the reset signal for the 20 MHz Oscillator and the source for nSYS_RST and nEC_RST.

As shown in Figure 7-18, Figure 7-20 and in Table 7-28, VTRGD is asserted following a delay after the VTR and

VTR_1.8 power supplies exceed preset voltage thresholds as defined in Table 7-25, “VTR/VBAT Reset Thresholds,” on

page 124. VTRGD is de-asserted as soon as either the VTR or VTR_1.8 power supplies drop below these thresholds

(see Figure 7-21, "VTR Power-Down Timing").

VTRGD can also be asserted as a result of a Watch-Dog Timer Forced Reset as described in Section 7.7.4, "Watch-

Dog Timer Forced Reset," on page 130, and by the RESETI# pin in the RESET Pin Interface.

FIGURE 7-19:

RESETI# TIMING

TABLE 7-27:

RESETI# TIMING PARAMETERS

Symbol

Parameter

Limits

Units

Comments

MIN

MAX

RESETI# Fall time

s

RESETI# Rise time

s

tRESET

Minimum Reset Time

s

Note 7-40

VSS

tRESET

0.8V

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