MEC1632 datasheet(128/636 Pages) MICROCHIP

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MEC1632

DS00001592B-page 128

 2012-2018 Microchip Technology Inc.

7.6.5

VBAT_POR

VBAT_POR occurs within the Reset Interface whenever the coin cell is replaced, or the VBAT voltage falls below 1.25

V nominal (Table 7-25).

There is also a VBAT_POR pulse external to the Reset Interface (Figure 7-20) that is used to reset VBAT powered status

bits in VTR powered registers. This pulse is asserted at the rising edge of nSYS_RST if a VBAT_POR was detected

within the Reset Interface when VTRGD was not asserted.

Note that both the 32.768 KHz Silicon Oscillator and the 32.768 KHz Crystal Oscillator are stopped if the coin cell is

replaced, or the VBAT voltage falls below 1.25 V nominal while VTRGD is not asserted. No action is taken if the coin

cell is replaced, or the VBAT voltage falls below 1.25 V nominal while VTRGD is asserted.

VBAT_POR is used as described throughout this specification to reset registers and functional device

blocks. VBAT_POR events are registered in the Power-Fail and Reset Status Register.

7.6.6

NSYS_RST

nSYS_RST is a combination of the following reset sources as described below: VTRGD, Watch-Dog Timer Forced

Reset, the RESETI# pin.

nSYS_RST is VTRGD synchronized to the 20 MHz Oscillator. Note that VTRGD and nSYS_RST have the same log-

ical sense (uninverted); however, because of nomenclature, the asserted states are opposite. Note that VTRGD is

defined in Section 7.6.4, "VTRGD," on page 126.

nSYS_RST is de-asserted as defined in Figure 7-20, "VTR Power-Up Timing" and in Table 7-28, "VTR Power-Up

Timing". nSYS_RST can also be asserted as a result of a Watch-Dog Timer Forced Reset as described in Section

7.7.4, "Watch-Dog Timer Forced Reset," on page 130, or when the RESETI# pin is asserted as described in Section

7.6.3, "RESET Pin Interface," on page 126. nSYS_RST is asserted as soon as either the VTR or VTR_1.8 power sup-

plies drop below preset voltage thresholds (see FIGURE 7-21: VTR Power-Down Timing on page 127).

nSYS_RST is the reset signal for all VTR-powered blocks except for the 20 MHz Oscillator and the Embedded

Controller. nSYS_RST also affects the VBAT-Powered Control Interface as described in Table 34-2, “VCI Output Truth

Table,” on page 501.

7.6.7

NEC_RST

nEC_RST is a delayed version of nSYS_RST that is used to reset the Embedded Controller and for Registers Interface

as described in Section 7.8, "Registers Interface," on page 130.

nEC_RST can be asserted as a result of a Watch-Dog Timer Forced Reset as described in Section 7.7.4, "Watch-Dog

Timer Forced Reset," on page 130, or when the RESETI# pin is asserted as described in Section 7.6.3, "RESET Pin

Interface," on page 126.Like nSYS_RST, nEC_RST is asserted as soon as either the VTR or VTR_1.8 power sup-

plies drop below preset voltage thresholds (see FIGURE 7-21: VTR Power-Down Timing on page 127).

nEC_RST is de-asserted as defined in Figure 7-20, "VTR Power-Up Timing" and in Table 7-28, "VTR Power-Up

Timing". nEC_RST is held asserted while the Gang Programmer Interfaceis activated.

7.7

1.8V Regulator

The 1.8V Regulator generates the MEC1632 core power well. As illustrated in Figure 7-18, "Reset Interface Block Dia-

gram", the input to the 1.8V Regulator is VTR, the output is VTR_1.8 (see also Table 7-4). The 1.8V Regulator is not

used when VTR is inactive, as described in Section 7.7.1, "Power Mux" below.

The stability of the 1.8V Regulator amplifier depends on an external capacitor, VR_CAP as described in Table 7-4.The

choice of capacitor can be either ceramic or low ESR tantalum. Ceramics are the recommended choice due to their

superior AC performance (below 100 m

 ESR), but X5R dielectrics should be used to prevent greater than 20% capac-

itance variation over temperature and voltage. Low ESR tantalum capacitors will work but care should be taken

because the ESR can vary 2x at low temperatures.

APPLICATION NOTE:

the 1.8V Regulator can be suspended in the SYSTEM DEEPEST SLEEP state using the

VREG SUS bit in the VREG Control Register on page 147.

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