MEC1632 datasheet(129/636 Pages) MICROCHIP

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 2012-2018 Microchip Technology Inc.

DS00001592B-page 129

MEC1632

7.7.1

POWER MUX

To provide the highest reliability and lowest possible power consumption, the Power Mux switches between the 1.8V

Regulator and a level-shifted VBAT voltage to produce the 1.8V internal supply for VBAT-backed logic (VTR1.8_BAT in

Table 7-4).

Power Mux switching depends on the voltage level of the 1.8V Regulator and the VTR supply. As illustrated in

Figure 7-18, the Power Mux selects the 1.8V Regulator after the VTR and the VTR_1.8 power supplies exceed preset

voltage thresholds. The Power Mux selects the VBAT supply as soon as either the VTR or VTR_1.8 power supplies

drop below these thresholds (see FIGURE 7-21: VTR Power-Down Timing on page 127).

Note that the Power Mux only switches 1.8 volts. To provide minimum VBAT power consumption for 3.3V VBAT pow-

ered outputs when VTR is fully powered, supply switching from VBAT to VTR must be done externally.

There is a separate power mux not shown in Figure 7-18 to ensure that the 32.768 KHz Silicon Oscillator is powered

when VTR is powered for TYPE 1 Power Supply Configurations.

7.7.2

VCC POWER GOOD

VCC Power Good is defined by the VCC_PWRGD input pin (Table 7-4). VCC_PWRGD is also synchronized to the 20

MHz Oscillator and used for the functions shown in Table 7-29.

The VCC_PWRGD input must always be driven to a ‘1’ or a ‘0,’ even when VCC is 0 V. The minimum VCC_PWRGD

pulse width (high and low) is shown below in Table 7-29.

7.7.3

LPC RESET

LPC RESET (LPC_RST# in Table 7-4) is defined by VCC_PWRGD, LRESET# and VTRGD as illustrated in Table 7-

31. LPC RESET only affects logic that is driven by PCI_CLK.

Note 7-42

this is the Table 7-4 VCC_PWRGD input.

Note 7-43

this is the Table 7-4 LRESET# input. The EC can determine the state of the LRESET# input using

registers in Table 6-8, “LPC Bus Monitor Register,” on page 90.

Note 7-44

see Section 7.6.4, "VTRGD," on page 126.

Note 7-45

LPC RESET is the Table 7-4 LPC_RST# output. The trailing edge of LPC_RST# is synchronized to

the PCI_CLK in Table 7-4.

TABLE 7-29:

VCC_PWRGD INPUT TIMING

Parameter

Symbol

MIN

TYP

MAX

Units

Notes

VCC_PWRGD Pulse Width

tVPGPW

–

TABLE 7-30:

FUNCTIONS AFFECTED BY

VCC Power Good

Name

Reference

Host Clock Domain

see Section 7.4.11.4, "Host Clock Domain," on page 120

LPC RESET

Section 7.7.3, "LPC RESET," on page 129

nSIO_RESET

"iRESET OUT," on page 133.

VCC_PWRGD_BUFF

Table 7-4, “Power, Clocks, and Resets Port List,” on page 96.

VCC_PWRGD

"VCC PWRGD," on page 133

TABLE 7-31:

LPC RESET DEFINITION

VCC_PWRGD

(

Note 7-42)

LRESET#

(

Note 7-43)

VTRGD

(

Note 7-44)

LPC RESET

(

Note 7-45)

Undefined

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