MEC1632 datasheet(133/636 Pages) MICROCHIP

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 2012-2018 Microchip Technology Inc.

DS00001592B-page 133

MEC1632

7.8.2

PCR STATUS AND CONTROL REGISTER

VCC PWRGD

The VCC PWRGD bit reflects the state of the synchronized VCC_PWRGD input pin (see Section 7.7.2, "VCC Power

Good," on page 129). The VCC PWRGD pin can generate an either-edge interrupt as described in the note associated

with the VCC PWRGD signal in Section 24.6, "GPIO Indexing," on page 391.

iRESET OUT

The iRESET OUT bit is used by firmware to control the nSIO_RESET signal function (Table 7-4). Firmware can pro-

gram the state of iRESET OUT except when the VCC PWRGD bit is not asserted (‘0’), in which case iRESET OUT is

‘don’t care’ and nSIO_RESET is asserted (‘0’) (Table 7-39). In all other cases, the nSIO_RESET signal function is

always the inverse of the iRESET OUT bit.

APPLICATION NOTE:

it should be noted that when the iRESET OUT bit is asserted (‘1’) the internal nSIO_RESET

is asserted even if the nRESET_OUT pin is configured as an alternate function.

Note 7-47

When the iRESET OUT bit is set to ‘1’, the falling edge of VCC PWRGD will cause the nRESET_OUT

signal function to be asserted within 15ns, A subsequent rising edge of VCC PWRGD will cause the

nRESET_OUT signal function to de-assert within 3 MCLKs.

Note 7-48

nSIO_RESET is also the source for the nRESET_OUT signal function.

FREQ LOCK

FREQ LOCK is asserted (‘1’) when the accuracy of the 20 MHz Oscillator is within the tightest tolerance described in

Table 7-6, “20 MHz Oscillator Timing Parameters,” on page 101.

TABLE 7-38:

PCR Status and Control Register

HOST

ADDRESS

N/A

N/A HOST SIZE

EC OFFSET

08h

32-bit EC SIZE

POWER

VTR

N/A nSYS_RST DEFAULT

BUS

EC SPB

BIT

D31

D30

D29

---

D10

HOST TYPE

––

–

EC TYPE

BIT NAME

Reserved

BIT

HOST TYPE

––

–

EC TYPE

R/W

BIT NAME

Reserved

FREQ

LOCK

iRESET

OUT

Reserved

VCC PWRGD

Reserved

TABLE 7-39:

iRESET OUT BIT BEHAVIOR

VCC PWRGD

iRESET OUT

nSIO_RESET &

nRESET_OUT

(See

Note 7-48)

Description

0 (ASSERTED)

The iRESET OUT bit does not affect the state of

nSIO_RESET when VCC PWRGD is not asserted.

0 (ASSERTED)

The iRESET OUT bit can only be written by firmware

when VCC PWRGD is asserted.

01 (NOT

ASSERTED)

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