MEC1632 datasheet(134/636 Pages) MICROCHIP

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MEC1632

DS00001592B-page 134

 2012-2018 Microchip Technology Inc.

7.8.3

CLOCK CONTROL REGISTER

SLEEP_FLAG

The SLEEP_FLAG affects the system power state as described in Section 7.4.10.2, "EC Controlled Dynamic Power

States," on page 112. The SLEEP_FLAG is R/W. EC firmware asserts SLEEP_FLAG (‘1’), which is then typically de-

asserted (‘0’) by hardware as described in Section 7.4.10.6, "Wake Interface," on page 118.

APPLICATION NOTE:

Asserting the SLEEP_FLAG allows the device to be put into lower power states as described

in Section 7.4.10.2, "EC Controlled Dynamic Power States," on page 112

. If the main

oscillator is shut down as a result of asserting the SLEEP_FLAG, then only the enabled wake

capable interrupts can restart the oscillator and bring the part out of its sleep state. When

the main oscillator is shut down, non-wake capable interrupts cannot occur. As part of the

wake process, the SLEEP_FLAG is cleared by hardware, re-enabling all blocks by de-

asserting all the block SLEEP_ENABLE signals as described in Section 7.4.10.5.4, "Block

Sleep Enables".

The typical sequence to go to sleep is this:

disable_interrupts();

assert_all_sleep_enables();

CLOCK_CONTROL_REGISTER->SLEEP_FLAG = 1;

_SLEEP();

where the macro _SLEEP() both enables interrupts and issues the ARC sleep instruction.

However, if any interrupt, including non-Wake interrupts, occurs just before the

SLEEP_FLAG is asserted, it will remain pending and will fire as soon as the ARC issues the

sleep instruction. The SLEEP_FLAG will remain asserted, and therefore all blocks are kept

in the low power state by their respective SLEEP_ENABLE signals. As a result, an interrupt

service routine may not proceed properly because blocks that it must manipulate remain in

their idle state.

If a system uses the sleep interface then every Interrupt Service Routine must manually clear

the SLEEP_FLAG. This ensures that all blocks that are supposed to be active when the ISR

is in process will be active.

TABLE 7-40:

Clock Control Register

HOST ADDRESS

N/A

N/A HOST SIZE

EC OFFSET

0Ch

32-bit EC SIZE

POWER

VTR

04h nSYS_RST DEFAULT

BUS

EC SPB

BIT

D31

D30

D29

---

D10

HOST TYPE

––

–

EC TYPE

RRR

BIT NAME

Reserved

BIT

D7D6D5

HOST TYPE

––

–

EC TYPE

R/W

BIT NAME

SLEEP CONFIG

WAIT

FOR

LOCK

32KHz

OUTPUT

MCHP

Reserved

SLEEP_F

LAG

Reserved

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