MEC1632 datasheet(135/636 Pages) MICROCHIP

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DS00001592B-page 135

MEC1632

32KHZ OUTPUT

The 32KHz OUTPUT bit controls the MEC1632 32KHZ_OUT signal function (Table 7-4).

0: The 32KHZ_OUTPUT clock output signal is enabled (default)

1: The 32KHZ_OUTPUT clock output signal is disabled. The 32KHZ_OUTPUT signal is driven low.

WAIT FOR LOCK

This bit controls the behavior of the system after a wake event occurs.

0: The system is clocked by the 10 MHz Ring Oscillator when a wake event occurs and switches to the 20 MHz Oscil-

latorwhen the FREQ LOCK bit is asserted. (default)

1: System clocking remains gated until the FREQ LOCK bit is asserted

SLEEP CONFIG

The SLEEP CONFIG field determines the latency following a wake event until the 20 MHz Oscillator is locked (FREQ

LOCK) and clocking the system. This latency is determined as defined in Table 7-41.

Note 7-49

Suspending the 1.8V Regulator also depends on the state of the VREG SUS bit in the VREG Control

TABLE 7-41:

SLEEP CONFIG BIT ENCODING

SLEEP CONFIG

Wake

Latency

Description

(

Note 7-49)

000

0 ns

Master Clock Trees, the 1.8V Regulator, the 20 MHz Oscillator, and the

regulator for the 20 MHz Oscillator all remain powered and running

during sleep cycles (SYSTEM HEAVY SLEEP 1) (DEFAULT)

200 ns

Master Clock Trees gated and the 1.8V Regulator is suspended during

sleep cycles. (SYSTEM HEAVY SLEEP 2)

460

s

Master Clock Trees gated, the 1.8V Regulator is suspended, and the 20

MHz Oscillator is stopped during sleep cycles. (SYSTEM HEAVY SLEEP

4.6 ms

Master Clock Trees gated, the 1.8V Regulator is suspended, the 20 MHz

Oscillator is stopped, and the regulator for the 20 MHz Oscillator is

powered down during sleep cycles. (SYSTEM DEEPEST SLEEP)

–

Reserved

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