MEC1632 datasheet(132/636 Pages) MICROCHIP

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MEC1632

DS00001592B-page 132

 2012-2018 Microchip Technology Inc.

7.8.1

EC CLOCK DIVIDER REGISTER

7.8.1.1

Overview

The Block Sleep Enable Registers (Table 7-36) contains the EC_CLK_DIV bits that are used to program the EC clock

and the EC_AHB clock enable frequency as described in Table 7-37.

EC_CLK_DIV

The EC_CLK_DIV bits contain the binary encoded divider that determines the EC clock and EC_AHB clock enable fre-

quency (Table 7-37). Writing ‘0’ to the Block Sleep Enable Registers has no effect. The EC_CLK_DIV default is 01h.

APPLICATION NOTE:

To support EC traffic to the LPC Subsystem, the EC_AHB clock frequency must be equal to

or less than the LPC_AHB clock frequency.

APPLICATION NOTE:

the JTAG clock cannot be higher than 1/2 the EC clock as defined by the EC Clock Divider

TABLE 7-36:

EC Clock Divider Register

HOST ADDRESS

N/A

N/A HOST SIZE

EC OFFSET

00h

32-bit EC SIZE

POWER

VTR

01h nSYS_RST DEFAULT

BUS

EC SPB

BIT

D31

D30

D29

---

D10

HOST TYPE

–

–––

––

–

EC TYPE

RRR

BIT NAME

Reserved

BIT

D6D5D4

D3D2

HOST TYPE

–

–––

––

–

EC TYPE

R/W

BIT NAME

Reserved

EC_CLK_DIV

TABLE 7-37:

EC_CLK_DIV ENCODING

EC_CLK_DIV

Nominal Frequency (MHz)

No Change

20.27 (default)

10.14

3h - Fh

Reserved

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