MEC1632 datasheet(130/636 Pages) MICROCHIP

130 / 636 page

MEC1632

DS00001592B-page 130

 2012-2018 Microchip Technology Inc.

7.7.4

WATCH-DOG TIMER FORCED RESET

A Watch-Dog Timer Forced Reset (Figure 7-22) occurs when the WDT_ALRT input (Table 7-4) is asserted (‘1’). As

shown in Figure 7-22, VTRGD is de-asserted (‘0’) and nSYS_RST and nEC_RST are asserted (‘0’) when WDT_ALRT

is asserted. The VTRGD reset time (tRST) is determined by the 32.768 KHz Silicon Oscillator as shown in Table 7-

32. Following the VTRGD reset time, the nSYS_RST Delay Time (tSYNC) and the nEC_RST Delay Time (tSTRETCH)

are determined using the 20 MHz Oscillator as described in Figure 7-20, "VTR Power-Up Timing" and Table 7-28, "VTR

Power-Up Timing".

Note that analog reset signal functions are not shown in Figure 7-22 because it is assumed that the power supplies are

fully powered and stable during a Watch-Dog Timer Forced Reset.

7.8

Registers Interface

The Power, Clocks, and Resets registers are located in two address ranges with two Base Address as indicated in

Table 7-33. See Note 4-1 on page 60.

Table 7-34 is a register summary for the Power, Clock & Reset (VTR PWR’ed) registers. Table 7-35 is a register sum-

mary for the Power, Clock & Reset (VBAT PWR’ed) registers

Each EC address is indicated as an SPB Offset from its AHB base address as indicated in Table 7-33.

The following tables summarize the registers allocated for each Instance. The offset field in the following table is the

offset from the Embedded Controller (EC) Base Address.

FIGURE 7-22:

Watch-Dog Timer Forced Reset TIMING

TABLE 7-32:

Watch-Dog Timer Forced Reset TIMING

Parameter

Symbol

MIN

TYP

MAX

Units

VTRGD Reset Time

tRST

1–

32.768 KHz Silicon Oscillator

Clock Cycles

nSYS_RST Delay Time

tSYNC

(see FIGURE 7-20: VTR Power-Up Timing on page 127)

nEC_RST Delay Time

tSTRETCH

TABLE 7-33:

POWER, CLOCKS AND RESETS INTERFACE BASE ADDRESS TABLE

Power, Clocks and Reset

Blocks

LDN from

(

Table 4-2 on

page 59)

AHB Base Address

Power, Clock & Reset (VTR

PWR’ed)

32h

F0_C800h

Power, Clock & Reset

(VBAT PWR’ed)

33h

F0_CC00h

VTRGD

nEC_RST

tRST

tSTRETCH

WDT_ALRT

nSYS_RST

tSYN

MEC1632 Datasheet(PDF) 130 Page - Microchip Technology

MEC1632 Datasheet(HTML) 130 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL