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MEC1632 Datasheet(PDF) 120 Page - Microchip Technology |
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MEC1632 Datasheet(HTML) 120 Page - Microchip Technology |
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120 / 636 page  MEC1632 DS00001592B-page 120 2012-2018 Microchip Technology Inc. 7.4.11 MCLK SOURCED CLOCKING 7.4.11.1 Overview MCLK Sourced Clocking includes all of the Fixed Clock Domain, Host Clock Domain and Programmable Clock Domains that are derived from the 20 MHz Oscillator. Ring Oscillator Sourced Clocking remains active as long as the 20 MHz Oscillator is running (see Section 7.4.10.4, "20 MHz Oscillator Control," on page 114). All MCLK Sourced Clocking and 32K Clock Domain clocking is summarized in Table 7-20. 7.4.11.2 Programmable Clock Domains 7.4.11.2.1 EC Bus Clock The EC Bus Clock (EC_BUS_CLK_EN) is a programmable clock that is derived from the Block Sleep Enable Registers as described in Section 7.8.4 on page 136. 7.4.11.2.2 LPC Bus Clock The LPC Bus Clock (LPC_BUS_CLK_EN) is a fixed clock. 7.4.11.3 Fixed Clock Domain The Fixed Clock Domain represents non-programmable clocks that are derived from the 20 MHz Oscillator. The Fixed Clock Domain outputs as shown in Table 7-20 are MCLK, MCLK_DIV2_EN, MCLK_DIV4_EN, MCLK_DIV10_EN, and MCLK_DIV203_EN. 7.4.11.4 Host Clock Domain The Host Clock Domain includes clocking for the Legacy Port Functions. Host Clock Domain clock gating is controlled by VCC_PWRGD such that when VCC_PWRGD is not asserted (‘0’), clocks in the Host Clock Domain are ‘off.’ When VCC_PWRGD is asserted (‘1’) clocks in the Host Clock Domain are ‘on’ and the Legacy Port Functions may be affected by the EC Controlled Dynamic Power States as described in Section 7.4.10, "Power Management Interface," on page 111. TABLE 7-20: ALL Clock Generator OUTPUT PORTS SUMMARY Symbol Type (Clock or Enable) Nominal Frequency Reference MCLK CLOCK 20.27 MHz Section 7.4.3, "20 MHz Oscillator," on page 100 EC_BUS_CLK_EN ENABLE Programmable "EC Bus Clock," on page 120 LPC_BUS_CLK_EN ENABLE 20.27 MHz "LPC Bus Clock," on page 120 MCLK_DIV1_EN ENABLE 20.27 MHz Section 7.4.11.3, "Fixed Clock Domain," on page 120 MCLK_DIV2_EN ENABLE 10.14 MHz MCLK_DIV4_EN ENABLE 5.07 MHz MCLK_DIV8_EN ENABLE 2.53 MHz MCLK_DIV10_EN ENABLE 2.03 MHz MCLK_DIV16_EN ENABLE 1.27 MHz MCLK_DIV20_EN ENABLE 1.01 MHz MCLK_DIV32_EN ENABLE 0.633 MHz MCLK_DIV64_EN ENABLE 317 KHz MCLK_DIV128_EN ENABLE 158 KHz MCLK_DIV203_EN ENABLE 99.852 KHz MCLK_5HZ_EN ENABLE 5 Hz MCLK_DIV20_EN_HST ENABLE 1.01 MHz Section 7.4.11.4, "Host Clock Domain," on page 120 X32K_CLK CLOCK 32.768 KHz Section 7.4.5, "32.768 KHz Silicon Oscillator," on page 102 |
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