MEC1632 datasheet(117/636 Pages) MICROCHIP

117 / 636 page

 2012-2018 Microchip Technology Inc.

DS00001592B-page 117

MEC1632

7.4.10.5.3

EC Controlled Sleep State Activation

OVERVIEW

EC Controlled Sleep State Activation depends upon the assertion of the ARC_CLK_DISABLE signal which occurs when

the EC executes a sleep instruction. The dynamic sleep states that can be achieved through EC Controlled Sleep

State Activation in part depend on the state of the SLEEP_FLAG in the Clock Control Register as defined in the sections

below, “Entering and Exiting EC Sleep State” and “Entering and Exiting System Sleep States.” Simultaneous asser-

tions of the WAKE input and EC Controlled Sleep State Activation immediately terminate system sleeps states as

defined in Section 7.4.10.6, "Wake Interface," on page 118.

ENTERING AND EXITING EC SLEEP STATE

As illustrated in Section TABLE 7-14:, "EC Controlled Dynamic Power States," on page 112, transitions to the EC SLEEP

state occur when the ARC_CLK_DISABLE signal is asserted (i.e., the EC enters the sleep state) while the SLEEP_-

FLAG in the Clock Control Register is not asserted (‘0’). The EC SLEEP state is terminated when an interrupt to the

EC occurs, as described in Section 7.4.10.6, "Wake Interface," on page 118.

The EC enters the sleep state when the SLEEP instruction is issued. The SLEEP instruction halts the CPU pipeline

and gates the processor clocks. The clocks to the ARC interrupt logic are not gated. As long as interrupts are enabled

in the ARC core STATUS register and at least one interrupt is enabled in the Interrupt Accelerator when the SLEEP

instruction is issued, the processor will wake up and process the interrupt service routine when the interrupt

triggers. On return from interrupt, the processor will execute the instruction immediately following the SLEEP instruc-

tion.

If it is necessary to enable a wakeup interrupt just before entering the sleep state, some care is required to insure that

the interrupt does not fire before the SLEEP instruction is issued. The ARC FLAG instruction should be used to enable

and disable interrupts and the FLAG and SLEEP instructions should be contiguous to insure that the SLEEP is in the

processor pipeline when interrupts are enabled and therefore executes before an interrupt can fire.

For more information on the FLAG and SLEEP instructions, see the ARCompactä ISA Instruction Set Architecture Pro-

grammer’s Reference

ENTERING AND EXITING SYSTEM SLEEP STATES

As illustrated in Section TABLE 7-14:, "EC Controlled Dynamic Power States," on page 112, transitions to the system

sleep states (i.e., sleep states other than EC SLEEP) occur when the ARC_CLK_DISABLE signal is asserted (i.e., the

EC enters the sleep state) while the SLEEP_FLAG in the Clock Control Register is asserted (‘1’). These states include

SYSTEM LIGHT SLEEP, SYSTEM HEAVY SLEEP 1 and SYSTEM DEEPEST SLEEP.

The system sleep states are terminated when a wake event occurs as described in Section 7.4.10.6, "Wake Interface,"

on page 118 Entering and Exiting System Sleep States is similar to Entering and Exiting EC Sleep State. Refer to

the section Entering and Exiting EC Sleep State for information about sleeping the EC.

Note that as described in Section 7.4.10.2, "EC Controlled Dynamic Power States," on page 112, the PREPARING SYS-

TEM SLEEP state in Table 7-14 occurs as soon as the SLEEP_FLAG is asserted, independent of the state of

ARC_CLK_DISABLE. The EC can optionally interrogate the Clock Required Status Registers to estimate the depth of

the sleep state, for example, before executing a sleep instruction. The EC can return to the FULL POWER state from

the PREPARING SYSTEM SLEEP state at any time before executing a sleep instruction by de-asserting the SLEEP_-

FLAG.

When the ring oscillator is shut down, the oscillator can only be restarted by the Wake Interface or by power cycling the

system. In order for the Wake Interface to operate, at least one wake capable interrupt must be enabled in the Interrupt

Aggregator. This class of interrupts is described in Section 17.3.5, "Wake Capable Interrupts," on page 294.

7.4.10.5.4

Block Sleep Enables

The Block Sleep Enables allow the EC firmware to determine which blocks will receive sleep commands as a result of

EC Controlled Sleep State Activation (see "Entering and Exiting System Sleep States," on page 117). The Block Sleep

Enables are configured using the Block Sleep Enable Registers (see Section 7.8.4, "Block Sleep Enable Registers," on

TABLE 7-18:

EC Power State Controls TIMING PARAMETERS

Parameter

Symbol

MIN

TYP

MAX

Units

System Sleep Setup Time

tSLP-SETUP

1–

–

EC Clock

MEC1632 Datasheet(PDF) 117 Page - Microchip Technology

MEC1632 Datasheet(HTML) 117 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL