MEC1632 datasheet(118/636 Pages) MICROCHIP

118 / 636 page

MEC1632

DS00001592B-page 118

 2012-2018 Microchip Technology Inc.

page 136) and behave as illustrated in Figure 7-15, "Block Sleep Enables Example" and Table 7-19, "Block Sleep

Enables Definition". There are three Block Sleep Enable Registers: two EC Blocks Sleep Enables Registers (see Sec-

tion 7.8.4.2 on page 137) and one LPC Blocks Sleep Enables Register (Section 7.8.4.1 on page 136).

Note 7-31

sleep enable for a single block as defined in Section 7.8.4, "Block Sleep Enable Registers," on

page 136.

Note 7-32

Clock Generator sleep enable output signal to a single block (SLEEP_EN) as defined in the Generic

Block Clocking Model.

7.4.10.6

Wake Interface

The Wake Interface terminates the sleep states illustrated in Table 7-14, “EC Controlled Dynamic Power States,” on

page 1121 and includes interrupts to the EC to transition from the EC SLEEP state, as well as wake events that can

restart the 20 MHz Oscillator and terminate the SYSTEM LIGHT SLEEP, SYSTEM HEAVY SLEEP 1, SYSTEM HEAVY

SLEEP 2, SYSTEM HEAVY SLEEP 3 and SYSTEM DEEPEST SLEEP states.

FIGURE 7-15:

Block Sleep Enables EXAMPLE

TABLE 7-19:

Block Sleep Enables DEFINITION

Sleep Enable

(

Note 7-31)

SLEEP_FLAG

(

Note 7-20)

Block SLEEP_EN

Signal

(

Note 7-32)

Description

Block not enabled for sleep, system is in FULL

POWER or EC SLEEP state.

Block not enabled for sleep, system is in PRE-

PARING SYSTEM SLEEP or SYSTEM LIGHT

SLEEP state.

Block enabled for sleep, system is in FULL

POWER or EC SLEEP state.

Block enabled for sleep, system is in PREPAR-

ING SYSTEM SLEEP, SYSTEM LIGHT

SLEEP, SYSTEM HEAVY SLEEP 1, SYSTEM

HEAVY SLEEP 2, SYSTEM HEAVY SLEEP 3

or SYSTEM DEEPEST SLEEP state.

SLEEP_PWM1

SLEEP_FLAG

PWM1_SLEEP_EN

SLEEP_SMB1

SMB1_SLEEP_EN

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