MEC1632 datasheet(115/636 Pages) MICROCHIP

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 2012-2018 Microchip Technology Inc.

DS00001592B-page 115

MEC1632

Note 7-25

OSC_SLEEP_ENABLE is illustrated in Figure 7-13 and indicates the status of all the “Core Clock

Required Status” outputs defined in the Generic Block Clocking Model and aggregated in the Clock

Required Status Registers and the SLEEP CONFIG field. For a description of the SLEEP CONFIG

signaling, see the SLEEP CONFIG field in Section 7.8.3, "Clock Control Register," on page 134.

Note 7-26

see "EC Power State Controls," on page 115 and Table 7-4 for a description of the SLEEP_STATE

signal.

Note 7-27

see Section 7.4.10.6, "Wake Interface," on page 118 and Table 7-4 for a description of the WAKE

signal.

Note 7-28

MCLK_OSC_EN is the 20 MHz Oscillator enable control illustrated in Figure 7-13.

7.4.10.5

Clock Gating

7.4.10.5.1

Overview

Power savings using the Power Management Interface comes from Clock Gating as described above and in the sub-

sections that follow. The magnitude of the power savings depends on the configuration of the Block Sleep Enables,

the SLEEP CONFIG field in the Clock Control Register, the configuration of the Master Clock Trees and the operational

status of the individual blocks as defined by the Clock Required Status Registers.

7.4.10.5.2

EC Power State Controls

Assuming WAKE is not asserted, when the SLEEP_FLAG bit in the Clock Control Register is asserted by the EC (see

also "EC Controlled Sleep State Activation," on page 117), a sleep command is sent to all blocks that are configured for

sleep as defined by the Block Sleep Enables. Clock Gating occurs at the block level following the sleep command

depending on the state of the block clocking requirement (see Section 7.8.5, "Clock Required Status Registers," on

page 140).

Once the SLEEP_FLAG bit is asserted, Clock Gating can only occur within the Clock Generator when the ARC_CLK_-

DISABLE signal (see Table 7-4, “Power, Clocks, and Resets Port List,” on page 96) is asserted, at which time the

SLEEP_STATE signal that can affect 20 MHz Oscillator Control is asserted (Table 7-17). Timing for the EC Power

State Controls is defined in Figure 6.7 and Table 6.11.

If WAKE is asserted when EC Controlled Sleep State Activation is attempted, the 20 MHz Oscillator will remain enabled,

the SLEEP_FLAG will be automatically de-asserted by hardware as described in Section 7.4.10.6, "Wake Interface," on

page 118 and an EC interrupt will occur (not shown in Table 7-17).

TABLE 7-16:

MCLK_OSC_EN CONTROL

OSC_SLEEP_

ENABLE

(

Note 7-25)

SLEEP_STATE

(

Note 7-26)

WAKE

(

Note 7-27)

MCLK_OSC_

EN (

Note 7-

28)

Description

The 20 MHz Oscillator is always enabled

(“on”) when at least one block requires the

clock or the EC has overridden the 20 MHz

Oscillator sleep state using the SLEEP

CONFIG field in the Clock Control Register.

The 20 MHz Oscillator is always enabled

(“on”) when SLEEP_STATE is not asserted.

The 20 MHz Oscillator is always enabled

(“on”) when WAKE is asserted.

20 MHz Oscillator is disabled (“off”) when

SLEEP_STATE is asserted, all blocks do

not require the 20 MHz Oscillator, the EC

has not overridden the 20 MHz Oscillator

sleep state using the SLEEP CONFIG field

and WAKE is not asserted.

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