| Electronic Components Datasheet Search |
|
MEC1632 Datasheet(PDF) 113 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
MEC1632 Datasheet(HTML) 113 Page - Microchip Technology |
|
113 / 636 page ![]() 2012-2018 Microchip Technology Inc. DS00001592B-page 113 MEC1632 Note 7-20 SLEEP_FLAG is bit D1 in the Clock Control Register. Note 7-21 the ARC_CLK_DISABLE signal is described in Table 7-4, “Power, Clocks, and Resets Port List,” on page 96. Note 7-22 includes the sum of all the “Core Clock Required Status” outputs defined in the Generic Block Clocking Model and aggregated in the Clock Required Status Registers. Note 7-23 this column refers to the SLEEP CONFIG field in the Clock Control Register. Note 7-24 In the PREPARING SYSTEM SLEEP state when the sleep enable to a block is asserted, EC register accesses to that block are undefined and should be avoided. SYSTEM LIGHT SLEEP 1 1 Clock Required X System is in a sleeping mode but the 20 MHz Oscillator must remain operating because one or more blocks require a clock. SYSTEM HEAVY SLEEP 1 Clock Not Required 0 System is in a sleeping mode and no blocks require the clock. There is no clock start up latency following a wake event in SYSTEM HEAVY SLEEP 1 (see Table 7-41, “SLEEP CONFIG Bit Encoding,” on page 135). SYSTEM HEAVY SLEEP 2 1 System is in a sleeping mode and no blocks require the clock. There is mini- mal clock start up latency following a wake event in SYSTEM HEAVY SLEEP 2 (see Table 7-41, “SLEEP CONFIG Bit Encoding,” on page 135). SYSTEM HEAVY SLEEP 3 2 System is in a sleeping mode and no blocks require the clock. There is more clock start up latency following a wake event in SYSTEM HEAVY SLEEP 3 than from SYSTEM HEAVY SLEEP 2 (see Table 7-41, “SLEEP CONFIG Bit Encoding,” on page 135). SYSTEM DEEPEST SLEEP 3 System is in a sleeping mode and no blocks require the clock. Clock start up latency is the longest and power consumption the lowest in SYSTEM DEEPEST SLEEP (see Table 7-41, “SLEEP CONFIG Bit Encoding,” on page 135). TABLE 7-14: EC CONTROLLED DYNAMIC POWER STATES (CONTINUED) Power State Name SLEEP_FLAG ( Note 7-20) ARC_CLK_ DISABLE ( Note 7-21) Global Block Clock Status ( Note 7-22) SLEEP CONFIG ( Note 7-23) Description |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |