MEC1632 datasheet(119/636 Pages) MICROCHIP

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 2012-2018 Microchip Technology Inc.

DS00001592B-page 119

MEC1632

The WAKE signal shown in Table 7-4, “Power, Clocks, and Resets Port List,” on page 96 is the only required input to

the Clock Generator for the Wake Interface. Wake Capable Interrupts, although technically part of the Wake Interface,

are external to the Power, Clocks, and Resets function and are not illustrated in this definition. The minimum pulse-

width for wake events is characterized in Table 24-1, “GPIO Interrupt/Wake Event Timing Parameters,” on page 390.

When the WAKE signal is asserted while a dynamic system sleep state is enabled, the SLEEP_FLAG in the Clock Con-

trol Register is automatically de-asserted by hardware within the first one or two clocks that occur when the 20 MHz

Oscillator is re-enabled as illustrated in Figure 7-16. As described in "EC Power State Controls," on page 115 and in

"EC Controlled Sleep State Activation," on page 117, system sleep states are essentially ignored if the SLEEP_STATE

signal and the WAKE signal are simultaneously asserted.

7.4.10.6.1

Treatment Of Non-wake Capable Interrupts During Sleep Transitions

There are two categories of Interrupts which effect the Wake Interface differently: Wake Capable Interrupts and Non-

Wake Capable Interrupts. See Section 17.3.5, "Wake Capable Interrupts," on page 294 in Section 17.0, "EC Interrupt

Aggregator".

The lowest power states in which Non-Wake Capable Interrupts can be asserted are PREPARING SYSTEM SLEEP or

SYSTEM LIGHT SLEEP. This is because the source of these interrupts require clocks to generate the interrupts. In the

event that the EC Controlled Dynamic Power States enters the PREPARING SYSTEM SLEEP or SYSTEM LIGHT

SLEEP state by the ARC executing a sleep instruction while a least one non-wake interrupt associated block is active,

the EC Controlled Dynamic Power States will not enter a lower state until a non-wake interrupt occurs. The non-wake-

able interrupt changes the ARC from a halt state to a running state to process the interrupt. Firmware needs to toggle

the state of the SLEEP_FLAG bit in the Clock Control Register. If these bit were Wake-up events, the firmware would

not need to de-assert the SLEEP_FLAG bit since hardware will have done so already.

APPLICATION NOTE:

if an aggressive sleep policy is implemented and firmware attempts to enter sleep when at

least one non-wake interrupt associated block is active, then firmware can treat all interrupt

identically (this includes both Wake Capable Interrupts or Non-Wake Capable

Interrupts). Firmware can service both Wake Capable Interrupts or Non-Wake Capable

Interrupts by attempting to toggle the SLEEP_FLAG in the Clock Control Register first ‘0’

then ‘1’ to prepare to sleep.

APPLICATION NOTE:

if a less aggressive sleep policy is implemented and firmware never attempts to enter sleep

when any non-wake interrupt associated block is active, then firmware can treat all Wake

Capable Interrupts identically. Firmware can service all Wake Capable Interrupts by

attempting setting the SLEEP_FLAG bit to ‘1’ in the Clock Control Register to prepare to

sleep.

FIGURE 7-16:

Wake Interface TIMING

WAKE

MCLK

ARC_CLK_DISABLE

SLEEP_FLAG

SLEEP_STATE

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