MEC1632 datasheet(121/636 Pages) MICROCHIP

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DS00001592B-page 121

MEC1632

The Host Clock Domain output as shown in Table 7-20 is MCLK_DIV20_EN_HST.

7.4.12

32K CLOCK DOMAIN

7.4.12.1

Overview

The 32K Clock Domain represents all of the clocking derived from the 32.768 KHz Silicon Oscillator, the 32.768 KHz

Crystal Oscillator or the external single-ended 32KHz clock input. The output 32.768 KHz clock source is synchronized

to the 20 MHz Oscillator as described below in Section 7.4.12.2, "Synchronization".

The 32K Clock Domain remains active as long as the selected 32.768 KHz clock source is running (see "32K_EN," on

page 149). The blocks driven by the 32K Clock Domain are summarized in Table 7-21 and are not affected by Clock

Gating in the Power Management Interface. Typically, blocks driven by the 32K Clock Domain can generate wake

events, even when the 20 MHz Oscillator is disabled.

7.4.12.2

Synchronization

The 32K Clock Domain X32K_CLK output is synchronized to the 20 MHz Oscillator. Synchronization is disabled under

two conditions: 1) when the 20 MHz Oscillator is disabled (e.g., in the SYSTEM DEEPEST SLEEP state or during a test

mode) and 2) when VTRGD is not asserted (see Section 7.6.4, "VTRGD," on page 126).

7.4.12.3

Summary

The distribution of the 32K Clock Domain throughout the MEC1632 is illustrated in Table 7-21, below.

Note 7-33

Synchronization as described in Section 7.4.12.2 does not apply to the output of the 32.768 KHz

Silicon Oscillator that is applied to the 20 MHz Oscillator.

7.5

Power Configuration

7.5.1

POWER SUPPLIES AND CLOCKS ACPI CONTEXT

The MEC1632 is influenced by three separate power planes, VBAT, VTR, and VCC, as described in Table 6.15.The

VBAT and VTR power planes provide power directly to the MEC1632 through the VBAT and VTR pins shown in Table 7-

4, "Power, Clocks, and Resets Port List". The MEC1632 senses the VCC power state using the VCC_PWRGD input

pin. The VBAT, VTR, and VCC power sequencing requirements are as follows (see also Section 7.5.3, "Power-Up

Sequence," on page 124):

VCC power can be applied simultaneously with or after VTR power.

VTR power can be applied simultaneously with or after VBAT.

The typical relationships of the MEC1632 power supplies to the system power states is shown below in

Table 6.15. The distribution of the MEC1632 power supplies to the various functional blocks is illustrated in FIGURE

2-1: MEC1632 Top-level Block Diagram on page 8.

The typical relationships of the MEC1632 clocks to the system power states is shown below in

Table 6.16. Descriptions of the various clock domains can be found in Section 7.4, "Clock Generator," on page 98.

TABLE 7-21:

32K Clock Domain DRIVEN BLOCKS

Block Name

Block Cross Reference

Week Timer

Section 22.0, "Week Alarm Interface," on page 370

Watch-Dog Timer

Section 18.0, "Watchdog Timer Interface," on page 330

Hibernation Timer 0

Section 21.0, "Hibernation Timer," on page 366

Hibernation Timer 1

LED Interface

Section 36.0, "Blinking/Breathing PWM," on page 510

Watch-Dog Timer Forced Reset

Section 7.7.4, "Watch-Dog Timer Forced Reset," on page 130

20 MHz Oscillator

Section 7.4.3, "20 MHz Oscillator," on page 100 (Note 7-33).

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