MEC1632 datasheet(148/636 Pages) MICROCHIP

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MEC1632

DS00001592B-page 148

 2012-2018 Microchip Technology Inc.

7.9

VBAT Powered Registers

7.9.1

POWER-FAIL AND RESET STATUS REGISTER

7.9.1.1

Overview

The Power-Fail and Reset Status Register collects and retains the VBAT RST, FLASH and WDT event status when VTR

is unpowered. Asserted events can cause interrupts as described in Section 7.10, "Interrupt Interface," on page 150.

DET32K_IN

WDT

The WDT bit is asserted (‘1’) following a Watch-Dog Timer Forced Reset as described in Section 7.7.4, "Watch-Dog

Timer Forced Reset," on page 130. To clear the WDT bit EC firmware must write a ‘1’ to this bit; writing a ‘0’ to the

WDT bit has no affect.

FLASH

The FLASH bit is set to ‘1’ by hardware when FLASH_PGM in Table 7-4, “Power, Clocks, and Resets Port List,” on

page 96 is asserted. FLASH_PGM is asserted when the Embedded Flash is placed in Program Mode or Erase

Mode. To clear the FLASH bit EC firmware must write a ‘1’ to this bit; writing a ‘0’ to the FLASH bit has no affect.

VBAT RST

The VBAT RST bit is set to ‘1’ by hardware when a VBAT_POR is detected. This is the register default value. To clear

VBAT RST EC firmware must write a ‘1’ to this bit; writing a ‘0’ to VBAT RST has no affect.

The Clock Enable Register AD_EN, 32K_EN, XTL32K_EN, XTL_SEL, and EXT32K_VBAT bits should not toggle on the

same write; i.e., only one bit should be updated at a time.

TABLE 7-58:

Power-Fail and Reset Status Register

HOST ADDRESS

N/A

N/A HOST SIZE

EC OFFSET

00h

32-bit EC SIZE

POWER

VBAT

1XX000Xb VBAT_POR

DEFAULT

BUS

EC SPB

BIT

D31

D30

D29

---

D10

HOST TYPE

–

–––––––

EC TYPE

RRRRR

BIT NAME

Reserved

BIT

D7D6D5D4D3D2D1D0

HOST TYPE

–

–––––––

EC TYPE

R/WC

RRRRR

BIT NAME

VBAT

RST

FLASH

WDT

Reserved

DET32K_I

TABLE 7-59:

DET32K_IN BIT ENCODING

DET32K_IN

Description

No clock detected on the 32KHZ_IN pin

Clock is detected on the 32KHZ_IN pin

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