MEC1632 datasheet(152/636 Pages) MICROCHIP

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MEC1632

DS00001592B-page 152

 2012-2018 Microchip Technology Inc.

8.3

Interrupts

Each instance of the Embedded Memory Interface can generate an interrupt event for the HOST-to-EC events. See

HOST-to-EC Mailbox Register on page 158. The interrupt source for the EMI is routed onto the EM_MBX bit in the

GIRQ15 Source Register and is edge-sensitive, active high.

When the EM_MBX interrupt status bit is cleared while there is data in the HOST-to-EC Mailbox Register, the interrupt

remains not asserted until the host writes another byte. If the host writes a second byte to the HOST-to-EC Mailbox

Register before the EC processes the EM_MBX interrupt resulting from the first byte, the data from the first byte will be

overwritten by the second before the EC has a chance to process the first. This can be avoided with a proper hand-

shaking protocol between the host and EC (for example, the EC should process a data in the HOST-to-EC Mailbox Reg-

ister before signaling the host that the data register is free).

8.3.1

EMBEDDED MEMORY INTERFACE SIRQ ROUTING

The Embedded Memory Interface can generate a SIRQ event for the EC-to-HOST EC events. See HOST-to-EC Mailbox

IRQ Configuration Registers on page 72). For this interrupt, the SELECT on page 72 is cleared to ‘0’ in the Interrupt

Configuration Register for the selected SIRQ frame.

The Embedded Memory Interface can also generate an event on an external pin, nEM_INT. The pin can be routed to

SMI or PME inputs, as required. The EC can cause the event to be generated by either writing the EC-to-Host Mailbox

routed to any frame in the SIRQ stream or to the external pin. To enable routing to the SIRQ stream, the bit SELECT on

page 72 is set to ‘1’ in the Interrupt Configuration Register for the selected SIRQ frame. The event can be routed to the

pin by selecting the nEM_INT signal function in the associated Pin Control Register on page 396.

The event produces a standard active low on the serial IRQ stream and active low on the open drain nEM_INT pin. See

FIGURE 8-2: Embedded Memory Interface SIRQ and nEM_INT routing on page 153.

See Section 5.7.1, "SERIRQ Configuration Registers," on page 72.

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