MEC1632 datasheet(156/636 Pages) MICROCHIP

156 / 636 page

MEC1632

DS00001592B-page 156

 2012-2018 Microchip Technology Inc.

Because there are two Embedded Memory Interface memory regions, the Embedded Memory Interface cannot be used

for more than two of these functions at a time. The Host can request that the EC switch from one function to another

through the use of the Host-to-EC mailbox register.

The Application ID Register is provided to help software applications track ownership of an Embedded Memory Inter-

face. An application can write the Application ID Register with its Application ID, then immediately read it back. If the

read value is not the same as the value written, then another application has ownership of the interface.

8.5

Registers

The Embedded Memory Interface has its own Logical Device Number, and Base Address as indicated in Table 8-1. The

Host LPC I/O addresses for the Embedded Memory Interface are selected via a Base Address Register (see Section

5.6.2, "Base Address Registers," on page 66). LPC access to configuration registers is through Host Access Configu-

ration Port (see Section 5.5.1, "Host Access Port," on page 65.)

Table 8-2 is a register summary for the Embedded Memory Interface block.

The Table 8-2 is a register summary for one instance of the Embedded Memory Interface. The LPC I/O address for each

Run-Time Register is described below as an offset from its Base Address Register. Each EC address is indicated as an

SPB Offset from its AHB base address. Each Configuration register is accessed through the Host Access Port is via its

LDN indicated in Table 8-1 on page 156 and its Host Access Port index which is described as “Host Config Index” in the

tables below.

Note:

• The protocol used to pass commands back and forth through the Embedded Memory Interface Registers Inter-

face is left to the System designer. Microchip can provide an application example of working code in which the

host uses the Embedded Memory Interface registers to gain access to all of the EC registers.

• The EC must be awake (i.e., the EC must not be in sleep mode with its clocks gated) in order for the EMI to read

or write data in the DCCM/ICCM. System software can insure that the EC is awake when the Host is accessing

the EMI with an appropriate protocol using the Host-to-EC mailbox register. Before accessing the memory, the

Host sends a “Do Not Sleep” command to the EC through the mailbox register. Writing the register generates an

EC interrupt, which wakes the EC. The “Do Not Sleep” command sets a state bit that the EC can check before it

issues the Sleep command. When the Host has completed accessing the memory, the Host sends a “Sleep Per-

mitted” command to the EC.

TABLE 8-1:

Embedded Memory Interface BASE ADDRESS TABLE

Embedded Memory

Interface Instance

LDN from

(

Table 4-2 on

page 59)

AHB Base Address

EM Interface

10h

FF_4000h

Note:

The Host LPC I/O addresses for this instance is selected via a Base Address Register (see Section 5.6.2,

"Base Address Registers," on page 66). LPC access to configuration registers is through the Host Access

Configuration Port (see Section 5.5.1, "Host Access Port," on page 65.)

TABLE 8-2:

Embedded Memory Interface REGISTER SUMMARY

Host I/O Access

EC Interface

Host I/O

Offset

SPB

Offset

Host

Type

SPB

Offset

Byte

Lane

Type

Notes

HOST-to-EC Mailbox

00h

R/W

00h

R/W

Note 8-1

EC-to-Host Mailbox

01h

R/WC

01h

R/WC

Note 8-2

EC Address Register

02h

03h

02h

03h

R/W

02h

2-3

R/W

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