MEC1632 datasheet(157/636 Pages) MICROCHIP

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 2012-2018 Microchip Technology Inc.

DS00001592B-page 157

MEC1632

Note 8-1

Interrupt is cleared when read by the EC.

Note 8-2

Interrupt is cleared when read by the host.

8.5.1

EMBEDDED MEMORY INTERFACE CONTROL REGISTERS

Mailbox Register, HOST-to-EC, and Mailbox Register, EC-to-HOST, are specifically designed to pass commands

between the host and the EC (FIGURE 8-1: on page 151). If enabled, these registers can generate interrupts.

When the host performs a write of the HOST-to-EC mailbox register, an interrupt will be generated and seen by the EC

if unmasked. When the EC writes the HOST-to-EC mailbox register using the EC-only offset address 100h, it can reset

the register to 00h, providing a simple means for the EC to inform the host that an operation has been completed.

When the EC writes the EC-to-HOST mailbox register, an SIRQ event or an event such as SMI or PME may be gener-

ated and seen by the host if unmasked. The Host CPU can reset the EC-to-HOST mailbox register to 00h, providing a

simple means for the host to inform that EC that an operation has been completed.

EC Data Register

04h

05h

06h

07h

04h

05h

06h

07h

R/W

04h

0-3

R/W

Interrupt Source Register

08h

09h

08h

09h

Table 8-9

08h

0-1

Table 8-9

Interrupt Mask Register

0Ah

0Bh

0Ah

0Bh

R/W

0Ah

2-3

R/W

Application ID Register

0Ch

R/W

0Ch

R/W

HOST-to-EC Mailbox

100h

R/WC

Note 8-1

EC-to-Host Mailbox

101h

R/W

Note 8-2

Memory Base Address 0

104h

0-3

R/W

Memory Read Limit 0

108h

0-1

R/W

Memory Write Limit 0

10Ah

2-3

R/W

Memory Base Address 1

10Ch

0-3

R/W

Memory Read Limit 1

110h

0-1

R/W

Memory Write Limit 1

112h

2-3

R/W

Interrupt Set Register

114h

0-1

R/W

Host Clear Enable

116h

2-3

R/W

PROGRAMMER’S NOTE:

The protocol used to pass commands back and forth through the Mailbox Registers

Interface is left to the System designer. Microchip can provide an application example

of working code in which the host uses the Mailbox registers to gain access to all of the

EC registers.

TABLE 8-2:

Embedded Memory Interface REGISTER SUMMARY (CONTINUED)

Host I/O Access

EC Interface

Host I/O

Offset

SPB

Offset

Host

Type

SPB

Offset

Byte

Lane

Type

Notes

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