SM8521 datasheet(12/56 Pages) SHARP

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SM8521

Processor status 1 (PS1)

The processor status PS1 is an 8-bit readable/

writable register and consists of eight flag bits.

These flags can be used as the condition codes for

the conditional branch instructions. When CPU

generates an interrupt, the content of processor

status PS1 and the value of program counter PC

automatically are pushed onto stack.

Bit 7

Bit 7 : Carry (C)

It indicates that generated a carry in operation.

Bit 6 : Zero (Z)

It indicates that the operation result is zero.

Bit 5 : Sign (S)

It indicates that the operation result is negative

(Sign bit = ‘1’).

Bit 4 : Overflow (V)

Executes the operation with the signed value. If

the operation result cannot indicate complement

on two, then the bit will be ‘1’.

Bit 3 : Decimal adjustment (D)

It indicates that the last arithmetic operation is a

subtraction.

Bit 2 : Half carry (H)

It indicates that generated a carry between bit 3

and 4.

Bit 1 : Bit (B)

It indicates that the result of the last bit

manipulation.

Bit 0 : Interrupt enable (I)

This is a flag which enables /disables all

maskable interrupt.

System configuration register (SYS)

The system configuration register SYS is an 8-bit

readable/writable register which sets the external

memory expansion modes and selects 8-bit/16-bit

stack pointer.

Bit 7

Bit 7 : Sets '0'

Bit 6 : Stack pointer configuration (SPC)

Bits 5 to 3 : Set '0'

Bits 2 to 0 : Memory configuration (MCNF2-0)

∗ : In ROM space (60 k bytes), the field beyond the internal

ROM is the external memory access field.

Stack pointer (SPL, SPH)

The stack pointer SPL, SPH are 8-bit readable/

writable register and show the stack address. The

bit SPC of the system configuration (SYS) specifies

whether the stack pointer is 8 (SPL only) or 16

(both SPL and SPH) bits long.

Program counter (PC)

The program counter (PC) is a pointer for program

memory and contains the starting address for the

next instruction.

The program counter PC is initialized to 1020H after

hardware reset. That is, the application program

starts executing from the address 1020H after

hardware reset.

BIT

8-bit (SPL only)

CONTENT

16-bit (both SPL, SPH)

SPC

MCNF2 MCNF1 MCNF0

BIT

CONTENT

000

External memory expansion disable.

110

External memory expansion mode

(64 k bytes

Other

combination

Do not use.

Bit 15

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