SM8521 datasheet(26/56 Pages) SHARP

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SM8521

IR0 (Interrupt request register 0)

The interrupt request register IR0 is an 8-bit

readable/writable register containing the setting for

enable/disable to accept interrupt sources.

Bit 7

Bit 7 : DMA interrupt request bit

Bit 6 : Timer 0 interrupt request bit

Bit 5 : Sets ‘0’.

Bit 4 : External interrupt request bit

Bit 3 : UART interrupt request bit

Bit 2 : Sets ‘0’.

Bit 1 : Sets ‘0’.

Bit 0 : LCD controller Interrupt Request bit

IR1 (Interrupt request register 1)

The interrupt request register IR1 is an 8-bit

readable/writable register containing the setting for

enable/disable to accept interrupt sources.

Bit 7

Bit 7 : Sets ‘0’.

Bit 6 : Timer 1 interrupt request bit

Bit 5 : Sets ‘0’.

Bit 4 : Clock interrupt request bit

Bit 3 : Sets ‘0’.

Bit 2 : PIO interrupt request bit

Bit 1 to 0 : Set ‘0’.

The interrupt request register IR0 and IR1 are also

used to wake up the chip from standby mode

(STOP mode, HALT mode) by setting the interrupt

to enable. If the interrupt enabled by the interrupt

request register IR0 and IR1 occurs, the chip will

wake up from standby mode. But also there are

interrupt sources which cannot use to wake up

from STOP mode. For more details, refer to

"Standby Function".

BIT

CONTENT

Disable

Enable

DMA TIM0

EXT UART

LCDC

TIM1

CLK

PIO

BIT

CONTENT

Disable

Enable

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SM8521 Datasheet(PDF) 26 Page - Sharp Corporation

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