SM8521 datasheet(24/56 Pages) SHARP

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SM8521

Table 3

SM8521 Interrupt Vectors Location and Their Priority

VECTOR LOCATION

INTERRUPT SOURCE

SYMBOL

PRIORITY∗

1000H

DMA

DMAINT

1002H

Timer 0

TIM0INT

1006H

External interrupt

EXTINT

1008H

UART transmit/receive complete

UARTINT

100EH

LCD controller

LCDCINT

1012H

Timer 1

TIM1INT

1016H

Clock

CKINT

101AH

Input/output port

PIOINT

101CH

Watchdog timer overflow

WDTINT

–

101EH

NMI, illegal instruction

NMIINT, ILLINT

–

∗ The priority levels determine the order in which the chip process simultaneous interrupts. It also denotes the priority level of

mask interrupts by setting the bits IM2-IM0 (bits 2-0 : PS0).

PS0 (Interrupt maskbit (IM) of processor status 0)

The bits IM2-IM0 can set the acceptable level for

interrupt. The maskable interrupt requested by CPU

is set 1 to 8 priority levels. These bits IM2-IM0

determine processing interrupts which priority

levels.

Bits 2 to 0 : Interrupt mask bits (IM2-IM0)

BIT

CONTENT

000

All maskable interrupts recognized.

001

All maskable interrupts recognized.

010

Maskable interrupts with 1 to 7 level

recognized.

011

Maskable interrupts with 1 to 6 level

recognized.

100

Maskable interrupts with 1 to 5 level

recognized.

101

Maskable interrupts with 1 to 4 level

recognized.

110

Maskable interrupts with 1 to 3 level

recognized.

111

Maskable interrupts with 1 to 2 level

recognized.

NOTE :

When an interrupt enables by interrupt mask bit, if all

interrupt conditions are setup, then the CPU starts to the

interrupt processing.

- 24 -

SM8521 Datasheet(PDF) 24 Page - Sharp Corporation

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